A 5.6GHz to 11.5GHz DCO for digital dual loop CDRs

Titus, W.; Kenney, J.G.

doi:10.1109/rfic.2011.5940678

Cited by 3 publications

(6 citation statements)

References 5 publications

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“…As shown in Fig. 4(b), compared to the conventional TC/V PPS settings, 3300ppm/°C [2] and 640mV at 25°C [1], the proposed scheme reduce the parasitic capacitance at high temperature. …”

Section: (Cgd1+cgd2) (Vp-vn) < -Vthmentioning

confidence: 94%

“…We also ignore the overlap capacitance without affecting the model effectiveness. In this model, the small-signal capacitance C EQ_S , when M1 is saturated, can be obtained as equation (1). Similarly, Figs.…”

Section: B Frequency Dependence On Lc-vco Amplitudementioning

confidence: 99%

“…It is also highly desirable that the PLL remains locked over a wide temperature range after initially being calibrated [1]- [4]. However, the oscillation frequency of an LC-VCO will decrease as the temperature increases and vice versa [2].…”

Section: Introductionmentioning

confidence: 99%

“…Once the frequency drift is beyond the coverage of the fine tuning band, the PLL will lose lock and the communication will be interrupted. To avoid this kind of failure, several solutions have been proposed which can be categorized into three main approaches: (I) Extending the fine tuning band coverage by increasing VCO gain [2]; (II) Reducing the frequency drift by adding redundancy into the LC-tank [1], [3]; (III) Optimizing the VCO control voltage during the coarse-tune calibration [4]. For the first solution, high VCO gain will increase the spur level and degrade the phase noise.…”

Section: Introductionmentioning

confidence: 99%

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A 12GHz 67% tuning range 0.37pS RJ<inf>rms</inf> PLL with LC-VCO temperature compensation scheme in 0.13μm CMOS

You

Huang

Chen

et al. 2014

2014 IEEE Radio Frequency Integrated Circuits Symposium

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This paper presents a PLL designed in 0.13µm CMOS for multi-data rate serial link applications. A novel temperature compensation scheme is proposed to reduce the LC-VCO temperature frequency drift without sacrificing the tuning range. Thus, the PLL covers a 5.6GHz to 13.4GHz tuning range by using just two VCO cores while remaining locked from -40°C to 85°C. At 25°C, the PLL has an RMS random jitter (RJ rms ) of 0.37pS at 11.44GHz. The integrated jitter is less than 0.7pS over the tuning range and varies less than 50fS over temperature. The PLL consumes 50.88mW of power from a 1.2V supply at 12GHz and 25°C.Index Terms -Phase-locked loops (PLL), voltagecontrolled oscillators (VCO), temperature frequency drift.

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“…As shown in Fig. 4(b), compared to the conventional TC/V PPS settings, 3300ppm/°C [2] and 640mV at 25°C [1], the proposed scheme reduce the parasitic capacitance at high temperature. …”

Section: (Cgd1+cgd2) (Vp-vn) < -Vthmentioning

confidence: 94%

Section: B Frequency Dependence On Lc-vco Amplitudementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 12GHz 67% tuning range 0.37pS RJ<inf>rms</inf> PLL with LC-VCO temperature compensation scheme in 0.13μm CMOS

You

Huang

Chen

et al. 2014

2014 IEEE Radio Frequency Integrated Circuits Symposium

View full text Add to dashboard Cite

show abstract

“…Ping-Hsuan Hsieh et al (2010), proposes PLL for GHz clock generation in large digital systems uses 65 nm CMOS technology [3]. Ward S. Titus and et al proposes 5.6 GHz to 11.5 GHz DCO for Digital Dual Loop CDRs for PLL [14]. Delvadiya Harikrushna et al [15], designed PLL with PFD using 45 nm CMOS technology.…”

Section: Literature Reviewmentioning

confidence: 99%

Design and Implementation of DPLL Using Microwind 3.1 Software

Deshmukh¹,

Dandare²

2017

IJARCSSE

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Abstract-Digital Phase locked loop (DPLL) is one of the most important devices in almost all the electronic systems. This paper introduces the design of DPLL using sub-micron 45nm CMOS technology and implemented using microwind 3.1 software. The Software microwind 3.1 is used to design and simulate an integrated circuit at physical description level. Two different frequencies are generated at different voltages and it is observed that as supply voltage reduces power consumption also reduces.

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A 12 GHz low-jitter LC-VCO PLL in 130 nm CMOS

You¹,

Chen²,

Feng³

et al. 2015

J. Inst.

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We present a wideband low-jitter LC-VCO phase-locked loop in 130 nm CMOS technology for high speed serial link applications. The PLL covers a 5.6 GHz to 13.4 GHz frequency range by using two LC-VCO cores with an RMS jitter of 370 fs. The single event effects testing is performed with a neutron beam at Los Alamos National Laboratory and no frequency disturbance is found over the test period. The PLL consumes 50.88 mW of power under a 1.2 V power supply.

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A 5.6GHz to 11.5GHz DCO for digital dual loop CDRs

Cited by 3 publications

References 5 publications

A 12GHz 67% tuning range 0.37pS RJ<inf>rms</inf> PLL with LC-VCO temperature compensation scheme in 0.13μm CMOS

A 12GHz 67% tuning range 0.37pS RJ<inf>rms</inf> PLL with LC-VCO temperature compensation scheme in 0.13μm CMOS

Design and Implementation of DPLL Using Microwind 3.1 Software

A 12 GHz low-jitter LC-VCO PLL in 130 nm CMOS

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A 5.6GHz to 11.5GHz DCO for digital dual loop CDRs

Cited by 3 publications

References 5 publications

A 12GHz 67% tuning range 0.37pS RJ<inf>rms</inf> PLL with LC-VCO temperature compensation scheme in 0.13&#x03BC;m CMOS

A 12GHz 67% tuning range 0.37pS RJ<inf>rms</inf> PLL with LC-VCO temperature compensation scheme in 0.13&#x03BC;m CMOS

Design and Implementation of DPLL Using Microwind 3.1 Software

A 12 GHz low-jitter LC-VCO PLL in 130 nm CMOS

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Product

Resources

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A 12GHz 67% tuning range 0.37pS RJ<inf>rms</inf> PLL with LC-VCO temperature compensation scheme in 0.13μm CMOS

A 12GHz 67% tuning range 0.37pS RJ<inf>rms</inf> PLL with LC-VCO temperature compensation scheme in 0.13μm CMOS