A 5.4mW 0.07mm<sup>2</sup> 2.4GHz Front-End Receiver in 90nm CMOS for IEEE 802.15.4 WPAN

Camus, M.; Butaye, B.; Garcia, Luc; Sie, M.; Pellat, B.; Parra, T.

doi:10.1109/isscc.2008.4523210

Cited by 17 publications

(13 citation statements)

References 3 publications

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“…The measured IIP 3 of CG path is +8dBm and the measured IIP 3 of CS path is +9dBm. The measured result shows significant improvement and can be comparable to other WSN LNAs [5][6][7][8].…”

Section: Measurement Resultssupporting

confidence: 67%

“…Thus, no headroom problem exists in this design due to no cascode devices, such that this DPNC architecture can be applied to any advance process with low supply voltage. Table I summaries the DPNC LNA and other similar LNA designs, including two subthreshold LNAs [5][6], two WSN LNAs [7][8], a highly linear LNA [9], a differential LNA with BAW filter [10] and an active-balun LNA with transformer using [11]. The power consumption is similar to other low power LNAs [5][6][7][8], but noise figure and IIP 3 of the DPNC LNA is much better than others.…”

Section: Measurement Resultsmentioning

confidence: 99%

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A low power high reliability dual-path noise-cancelling LNA for WSN applications

Hsu

Wang

2010

IEEE Custom Integrated Circuits Conference 2010

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This paper presents a dual-path noise-cancelling (DPNC) LNA, which is designed for low power wireless sensor network (WSN) applications and operates at 2.4GHz band. The proposed DPNC LNA can effectively cancel internal circuit noise while consuming less power by g m -boosted technique. The measured voltage gain and NF are 22dB and 3.7dB, respectively. IIP 3 is +8dBm and consumes 1.2mW with a 1.0V single supply. Fabricating in the 0.18ȝm standard CMOS process, the LNA occupies an active area of 0.3mm 2 .

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“…The measured IIP 3 of CG path is +8dBm and the measured IIP 3 of CS path is +9dBm. The measured result shows significant improvement and can be comparable to other WSN LNAs [5][6][7][8].…”

Section: Measurement Resultssupporting

confidence: 67%

Section: Measurement Resultsmentioning

confidence: 99%

A low power high reliability dual-path noise-cancelling LNA for WSN applications

Hsu

Wang

2010

IEEE Custom Integrated Circuits Conference 2010

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“…The primary design goal for the receive path is to achieve excellent channel selectivity and dynamic range combined with good sensitivity at very low power consumption, all of which are important parameters for the reliable operation of WSN in the harsh 2.4GHz ISM band. The receiver uses a direct-conversion architecture and offers up to 20dB improved interference rejection in the adjacent channels compared to recently published WPAN transceivers based on the low-IF architecture [1,2]. Further emphasizing WSN reliability, the receiver supports switched antenna diversity to mitigate multipath fading.…”

mentioning

confidence: 99%

A highly integrated low-power 2.4GHz transceiver using a direct-conversion diversity receiver in 0.18µm CMOS for IEEE802.15.4 WPAN

Retz

Shanan

Mulvaney

et al. 2009

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

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The IC presented in this paper is a highly integrated low-power RF transceiver for wireless sensor networks (WSN) compliant with the IEEE 802.15.4 2.4GHz WPAN standard. It contains a radio controller with sleep timer and can perform higher-level MAC functions such as beacon detection and network timing synchronisation autonomously, thereby enabling significant power savings in the overall system. The primary design goal for the receive path is to achieve excellent channel selectivity and dynamic range combined with good sensitivity at very low power consumption, all of which are important parameters for the reliable operation of WSN in the harsh 2.4GHz ISM band. The receiver uses a direct-conversion architecture and offers up to 20dB improved interference rejection in the adjacent channels compared to recently published WPAN transceivers based on the low-IF architecture [1,2]. Further emphasizing WSN reliability, the receiver supports switched antenna diversity to mitigate multipath fading. Implemented in a 1P6M 0.18µm RFCMOS process, the IC occupies a die area of less than 5.9mm 2 . It operates with a supply voltage from 1.8V to 3.6V, draws 16.8mA in receive mode and 18mA when transmitting at 3dBm. Figure 24.4.1 shows the chip-level block diagram. The analog, VCO, synthesizer and digital sections are supplied by separate on-chip LDO regulators.Configuration data is retained in a 1.8V backup RAM, which is supplied by an ultra-low-power LDO. The radio controller is based on a power-and area-efficient custom MCU core with optimised instruction set. An amplitude-regulated 26MHz crystal oscillator acts as a calibration reference for the 32kHz RC oscillator. The transceiver is equipped with 2 differential RF ports. The 1 st port is an LNA input only. It has an LNA isolation switch (SW) to attenuate the input signal during the offset correction phase. The 2 nd port is shared between PA and LNA. The transmitter uses direct closed-loop VCO modulation through a fractional-N synthesizer. The bandwidth of the synthesizer is widened with a digital pre-emphasis filter, so that emissions and TX EVM specifications are met simultaneously. The VCO is running at twice the LO frequency to minimise LO self-mixing and pulling effects caused by interferers. The LNA is followed by a passive current-mode quadrature mixer. The input of each transimpedance amplifier (TIA) forms a summing node for the baseband side of the mixer switch pair and 2 current mode DACs which are part of the offset correction loop (OCL).A 3 rd -order 0.25dB-ripple Chebychev filter with 1.3MHz bandwidth attenuates interferers in the ADC sampling image at 13MHz by more than 65dB, and attenuates interferers in the adjacent channel at 5MHz offset by more than 40dB. A 3 rd -order digital IIR filter attenuates signals in the adjacent channel by an additional 35dB while maintaining an overall EVM of less than 5%. The PGA section provides 24dB of gain with 3dB steps and is followed by power-optimised 6b pipeline ADCs. The total voltage gain from antenna to the PGA output...

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“…3, the 3-port measurements are carried out. At differential output, the measurement buffer of [4] and [5] composed of a common source transistor pair cross-stacked with a source follower pair is used. Since the measurement buffer has unit voltage gain and high linearity (IIP3 and IIP2) not to affect the linearity of the proposed S-to-D LNA under 50 ohm loading, the measured power gain (S21) and linearity do not need to be de-embedded with those of the measurement buffer.…”

Section: Resultsmentioning

confidence: 99%

A CMOS resistive feedback single to differential low noise amplifier with multiple-tuner-outputs for a digital TV tuner

Im¹,

Nam

Song³

et al. 2009

2009 IEEE Radio Frequency Integrated Circuits Symposium

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A CMOS resistive feedback single to differential low noise amplifier (S-to-D LNA) with singleended multiple tuner outputs (MTOs) is implemented for a digital TV (DTV) tuner using a 0.18-µ µ µ µm CMOS process. In order to achieve wideband output balancing with high gain, low noise figure (NF) and high linearity, the S-to-D LNA exploiting the resistive feedback with enhanced loop gain is proposed. The proposed S-to-D LNA also has single-ended MTOs which are made by combining the differential output of the S-to-D LNA without second-order distortion for supporting multiple tuner and multiple stream applications. This leads the excellent IIP2 at both differential output and single-ended MTOs of the proposed S-to-D LNA. A voltage gain of 19.5 dB, an average NF of 2.4 dB, an IIP3 of -2 dBm and an IIP2 of 26 dBm are obtained at differential output. At single-ended MTOs, a voltage gain of 12.5 dB, an average NF of 2.9 dB, an IIP3 of -1.5 dBm and an IIP2 of 25 dBm are obtained.

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A 5.4mW 0.07mm² 2.4GHz Front-End Receiver in 90nm CMOS for IEEE 802.15.4 WPAN

Cited by 17 publications

References 3 publications

A low power high reliability dual-path noise-cancelling LNA for WSN applications

A low power high reliability dual-path noise-cancelling LNA for WSN applications

A highly integrated low-power 2.4GHz transceiver using a direct-conversion diversity receiver in 0.18µm CMOS for IEEE802.15.4 WPAN

A CMOS resistive feedback single to differential low noise amplifier with multiple-tuner-outputs for a digital TV tuner

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A 5.4mW 0.07mm2 2.4GHz Front-End Receiver in 90nm CMOS for IEEE 802.15.4 WPAN

Cited by 17 publications

References 3 publications

A low power high reliability dual-path noise-cancelling LNA for WSN applications

A low power high reliability dual-path noise-cancelling LNA for WSN applications

A highly integrated low-power 2.4GHz transceiver using a direct-conversion diversity receiver in 0.18&#x00B5;m CMOS for IEEE802.15.4 WPAN

A CMOS resistive feedback single to differential low noise amplifier with multiple-tuner-outputs for a digital TV tuner

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Product

Resources

About

A 5.4mW 0.07mm² 2.4GHz Front-End Receiver in 90nm CMOS for IEEE 802.15.4 WPAN

A highly integrated low-power 2.4GHz transceiver using a direct-conversion diversity receiver in 0.18µm CMOS for IEEE802.15.4 WPAN