A 5.3 pJ/Spike CMOS Neural Array Employing Time-Modulated Axon-Sharing and Background Mismatch Calibration Techniques

Design of a 180 nm CMOS Neuron Circuit with Soft‐Reset and Underflow Allowing for Loss‐Less Hardware Spiking Neural Networks

“…On the other hand, with regard to UFA functionality, several existing studies have either naturally implemented it or identified cases where this functionality is activated only under specific conditions. [ 27–31 ] However, there were no mentions or analyses of the significance of this functionality.…”

“…While many studies have favored reduced membrane capacitance and V DD to achieve lower area and energy consumption per spike, our proposed I&F neuron circuit exhibits relatively higher area and energy consumption per spike in its current prototype stage. [26][27][28][29][30][31] However, through careful circuit optimization in simulation, we achieved a remarkable reduction of %47.2% in the neuron's area and an impressive 90% decrease in energy consumption per spike.…”

“…On the other hand, with regard to UFA functionality, several existing studies have either naturally implemented it or identified cases where this functionality is activated only under specific conditions. [27][28][29][30][31] However, there were no mentions or analyses of the significance of this functionality. While the proposed circuit was implemented using a 180 nm CMOS technology, we anticipate that even more significant reductions in both the area and energy consumption per spike can be achieved using more advanced CMOS processes.…”