A 4Rx, 4Tx Ka-band transceiver in 40nm bulk CMOS technology for satellite terminal applications

Wong, Alan Chi-Wai; Devita, Gabriele; Wu, Shi-Ming; Lauria, Franco; Eid, Majd; Illuromi, Omotade; Ogunkunle, Samson; Modigliana, Alessandro

doi:10.1109/rfic51843.2021.9490428

Cited by 10 publications

(3 citation statements)

References 4 publications

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“…Figure 11 shows the chip micrographs of the basic ILFD, ILFD with a peaking inductor, and ILFD with a varactor. The chip sizes were 0.62 × 0.58 mm 2 , 0.67 × 0.58 mm 2 , and 0.66 × 0.55 mm 2 , respectively, excluding the probing pads. All chips consumed 26.1 mW of DC power.…”

Section: Frequency Divider Chainmentioning

confidence: 99%

“…The development of mobile devices and the need for high-speed communication have resulted in considerable research on receivers operating in the mm-wave frequency bands [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]. In [2][3][4], the beamforming receivers were implemented by combining four channels [2,3] and eight channels [4], respectively. In [5,6], direct-conversion receivers were presented for low power consumption and small chip area.…”

Section: Introductionmentioning

confidence: 99%

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A Q-Band CMOS Image-Rejection Receiver Integrated with LO and Frequency Dividers

Lee

Jeon

2023

Electronics

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This paper presents a Q-band image-rejection receiver using a 65 nm CMOS technology. For a high image-rejection ratio (IMRR), the Q-band receiver employs the Hartley architecture which consists of a Q-band low-noise amplifier, two down-conversion mixers, a 90° hybrid coupler, and two IF baluns. In addition, a Q-band fundamental voltage-controlled oscillator (VCO) and a frequency divider chain divided by 256 are integrated into the receiver for LO. A charge injection technique is employed in the mixers to reduce the DC power while maintaining a high conversion gain and linearity. The VCO adopts a cross-coupled topology to secure stable oscillation with high output power in the Q-band. The frequency divider chain is composed of an injection-locked frequency divider (ILFD) and a multi-stage current-mode logic (CML) divider to achieve a high division ratio of 256, which facilitates the LO signal locking to an external phase-locked loop. An inductive peaking is employed in the ILFD to widen the locking range. The Q-band image-rejection receiver exhibits a peak conversion gain of 16.4 dB at 43 GHz. The IMRR is no less than 35.6 dBc at the IF frequencies from 1.5 to 5 GHz.

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Section: Frequency Divider Chainmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Q-Band CMOS Image-Rejection Receiver Integrated with LO and Frequency Dividers

Lee

Jeon

2023

Electronics

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“…Radio frequency (RF) [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25] and local oscillator (LO) [26], [27], [28], [29], [30] phase-shifting (PS) architectures are widely utilized in phased-array systems due to the potentiality on high system efficiency. As shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

A Phase-Modulation Phase-Shifting Phased-Array Transmitter With Phase Self-Calibration and Deep PBOs Efficiency Enhancement

Zhou,

Yang,

Shu

et al. 2024

IEEE J. Solid-State Circuits

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In this article, a digital phase-modulation (PM) phase-shifting (PS) phased-array transmitter is proposed. Both PM and PS are implemented in a PS modulator. Meanwhile, a self-calibration loop is introduced in the PS modulator for improved phase linearity and minimized phase error. The phase control voltages for the PS modulator are generated from the self-calibration loop based on the output signals and reference signals. To reduce the calibration time, a capacitor-array-based state store memory is introduced in the self-calibration loop. Efficiency at 2.5-/6-/12-dB power back-off (PBO) is enhanced by class-G Doherty switched-capacitor power amplifier (SCPA). As a verification of the concept, a 2.1-2.9-GHz four-element phasedarray transmitter is designed and fabricated in a conventional 40-nm CMOS technology. The transmitter features a 10-bit fastlocking phase self-calibration with measured 0.4 • rms phase error and 0.2-dB rms power error. The measured peak saturated output power of each element is 26.95 dBm at 2.4 GHz. Besides, the measured system efficiency at 0-/2.5-/6-/12-dB PBO is 37.25%/34.24%/30.12%/21.23%. For 20-MHz 64-QAM/15-MHz 256-QAM modulation signal, it exhibits EVM of 4.65%/2.84%, average output power of 19.91/16.59 dBm, and average system efficiency of 24.12%/19.21% at 2.4 GHz. By connecting monopole antenna units with a gain of 4.21 dBi, the measured peak effective isotropic radiated power (EIRP) of phased-array transmitter is 42.05 dBm.

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A 27-to-31.6 GHz 8-Element Phased-Array Transmitter Front-End with Inter-Element-Interference Cancellation Scheme in 65 nm CMOS

Li,

Deng,

et al. 2023

2023 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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A 4Rx, 4Tx Ka-band transceiver in 40nm bulk CMOS technology for satellite terminal applications

Cited by 10 publications

References 4 publications

A Q-Band CMOS Image-Rejection Receiver Integrated with LO and Frequency Dividers

A Q-Band CMOS Image-Rejection Receiver Integrated with LO and Frequency Dividers

A Phase-Modulation Phase-Shifting Phased-Array Transmitter With Phase Self-Calibration and Deep PBOs Efficiency Enhancement

A 27-to-31.6 GHz 8-Element Phased-Array Transmitter Front-End with Inter-Element-Interference Cancellation Scheme in 65 nm CMOS

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