A 4H-SiC p-channel insulated gate bipolar transistor with higher breakdown voltage and superior V _F·C _res figure of merit

Abstract

A silicon carbide p-channel insulated gate bipolar transistors (IGBTs) with higher breakdown voltage (BV) and low VF·Cres figure of merit (FOM) have been simulated, fabricated, and characterized successfully. The proposed IGBT adds two n-type implant regions in the junction field effect transistor (JFET) area and increases gate oxide thickness above the JFET area to reduce the reverse transfer capacitance (Cres) and gate oxide electric field (Eox).The proposed structure notably lowers Eox below 3 MV/cm while elevating BV to 16.6 kV. A new FOM of VF·Cres is defined to evaluate the trade-off between the on-state and the Cres characteristics. Experimental results demonstrate that a lower VF·Cres FOM of 0.369 V·pF is achieved from the proposed IGBT with a reduction of 66.4%, compared to the conventional Current Spreading Layer (CSL) IGBT. Meanwhile, the simulated turn-on and turn-off time of the proposed IGBT reduce by 29.4% and 20%, respectively.