A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction

Fritsch, Alexander; Kugel, Michael; Sautter, R.; Wendel, D.; Pille, J.; Torreiter, O.; Kalyanasundaram, Shankar; Dobson, Daniel

doi:10.1109/esscirc.2015.7313897

Cited by 9 publications

(4 citation statements)

References 6 publications

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“…Four different memory sizes are considered: 64 × 64, 128 × 128, 192 × 192 and 256 × 256, intended as rows and columns. These values have been chosen to estimate how the array performance scales with its size, with size values usually adopted in literature for test chips [32,[36][37][38]. In Table 3, the energy-delay products values are shown, using as reference case the 256 × 256 array of Figure 19.…”

Section: Resultsmentioning

confidence: 99%

Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories

et al. 2021

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The speed of modern digital systems is severely limited by memory latency (the “Memory Wall” problem). Data exchange between Logic and Memory is also responsible for a large part of the system energy consumption. Logic-in-Memory (LiM) represents an attractive solution to this problem. By performing part of the computations directly inside the memory the system speed can be improved while reducing its energy consumption. LiM solutions that offer the major boost in performance are based on the modification of the memory cell. However, what is the cost of such modifications? How do these impact the memory array performance? In this work, this question is addressed by analysing a LiM memory array implementing an algorithm for the maximum/minimum value computation. The memory array is designed at physical level using the FreePDK 45nm CMOS process, with three memory cell variants, and its performance is compared to SRAM and CAM memories. Results highlight that read and write operations performance is worsened but in-memory operations result to be very efficient: a 55.26% reduction in the energy-delay product is measured for the AND operation with respect to the SRAM read one. Therefore, the LiM approach represents a very promising solution for low-density and high-performance memories.

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Section: Resultsmentioning

confidence: 99%

Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories

et al. 2021

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“…Rather, a C++ std::map is used. The address retrieved from the respective memory structure is then applied to access static random access memory (SRAM) as in Fritsch et al ( 2015 ), which in turn contains a digital word with bit positions encoding activity of the different outputs as in Zamarreno-Ramos et al ( 2013 ). 5 If the combination of TCAM and SRAM forms a shared connection memory, 6 only one input can be granted access to this memory per clock cycle, so that a need for arbitration between the inputs arises.…”

Section: Methodsmentioning

confidence: 99%

NoC simulation steered by NEST: McAERsim and a Noxim patch

Robens,

Kleijnen,

Schiek

et al. 2024

Front. Neurosci.

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IntroductionGreat knowledge was gained about the computational substrate of the brain, but the way in which components and entities interact to perform information processing still remains a secret. Complex and large-scale network models have been developed to unveil processes at the ensemble level taking place over a large range of timescales. They challenge any kind of simulation platform, so that efficient implementations need to be developed that gain from focusing on a set of relevant models. With increasing network sizes imposed by these models, low latency inter-node communication becomes a critical aspect. This situation is even accentuated, if slow processes like learning should be covered, that require faster than real-time simulation.MethodsTherefore, this article presents two simulation frameworks, in which network-on-chip simulators are interfaced with the neuroscientific development environment NEST. This combination yields network traffic that is directly defined by the relevant neural network models and used to steer the network-on-chip simulations. As one of the outcomes, instructive statistics on network latencies are obtained. Since time stamps of different granularity are used by the simulators, a conversion is required that can be exploited to emulate an intended acceleration factor.ResultsBy application of the frameworks to scaled versions of the cortical microcircuit model—selected because of its unique properties as well as challenging demands—performance curves, latency, and traffic distributions could be determined.DiscussionThe distinct characteristic of the second framework is its tree-based source-address driven multicast support, which, in connection with the torus topology, always led to the best results. Although currently biased by some inherent assumptions of the network-on-chip simulators, the results suit well to those of previous work dealing with node internals and suggesting accelerated simulations to be in reach.

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“…Therefore, in this example, 'L' holds the inverted value of S1, i.e., 0. Before the 10 (iso-I OFF ) 47 12 % 14 nm Bulk-FinFET [12] 1 ×15 300 99 39 % 14 nm Fe-FinFET [12] 1 ×15 300 305 64 % 14 nm SOI-FinFET [13] 128 ×32 300 150 -28 nm Bulk-CMOS [14] 1024 ×80 300 1700 -65 nm Bulk-CMOS [15] 2048 ×72 300 1900 -…”

Section: A Tcam Arrays For Hamming Distance Computation 1) Single Tca...mentioning

confidence: 99%

Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs

Parihar,

Thomann,

Pahwa

et al. 2023

IEEE Open J. Circuits Syst.

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Cryogenic CMOS circuits that efficiently connect the classical domain with the quantum world are the cornerstone in bringing large-scale quantum processors to reality. The major challenges are, however, the tight power budget (in the order of milliwatts) and small latency (in the order of microseconds) requirements that such circuits inevitably must fulfill when operating at cryogenic temperatures. In-memory computing (IMC) is rapidly emerging as an attractive paradigm that holds the promise of performing computations efficiently where the data does not need to move back and forth between the CPU and the memory. Hence, it overcomes the fundamental bottleneck in classical von Neumann architectures, which provides considerable savings in power and latency. In this work, for the first time, we propose and implement an end-to-end approach that investigates SRAM-based IMC for cryogenic CMOS. To achieve that, we first characterize commercial 5 nm FinFETs from 300 K down to 10 K. Then, we employ the first cryogenic-aware industry-standard compact model for the FinFET technology (BSIM-CMG) to empower SPICE to accurately capture how cryogenic temperatures alter the electrical characteristics of transistors (e.g., threshold voltage, carrier mobility, sub-threshold slope, etc.). Our key contributions span from (1) carefully calibrating the cryogenic-aware BSIM-CMG against commercial 5 nm FinFET measurements in which SPICE simulations come with an excellent agreement with the experimental data, (2) exploring how the robustness of SRAM cells against noise (during the hold, read, and write operations) changes at extremely low temperatures, (3) investigating how the behavior of SRAM-based IMC circuits changes at 10 K compared to 300 K, and (4) modeling the error probabilities of IMC circuits that are used to calculate the Hamming distance, which is one of the essential similarity calculations to perform classifications.

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A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction

Cited by 9 publications

References 6 publications

Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories

Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories

NoC simulation steered by NEST: McAERsim and a Noxim patch

Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs

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