A 480-MHz to 1-GHz sub-picosecond clock generator with a fast and accurate automatic frequency calibration in 0.13-&amp;#x00B5;m CMOS

Lee, Joon‐Hee; Kim, Kyunglok; Lee, Junghyup; Jang, Taekwang; Cho, Seonghwan

doi:10.1109/asscc.2007.4425733

Cited by 12 publications

(4 citation statements)

References 9 publications

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“…Compare to the open-loop calibration based on frequency comparison, this method only costs several clock cycles before comparing, which shorten the calibration time to several us. The calibration time with period comparison is reduced to several us or sometimes sub-us, such as 4us in [11] and 0.35us in [12] with inter-N PLL. The typical locking process of PLL, suppose its LC VCO has a 3-bit cap bank, based on closed-loop calibration and open-loop calibration as discussed above are illustrated in Fig.5 respectively.…”

Section: Closed-loop Afc Technique Based On Vctrl Monitoringmentioning

confidence: 99%

An ultra-fast and high-precision VCO frequency calibration technique for fractional-N frequency synthesizers

Liu

Gan

2020

IEICE Electron. Express

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A novel VCO auto frequency calibration(AFC) technique is presented in this paper. It provides ultra-fast and high-precision search for an optimum VCO discrete tuning curve among a group of frequency sub-bands in the PLL frequency synthesizer. The calibration circuit consists of a table of frequency (TOF) and a finite state machine (FSM). Asynchronous work of TOF and FSM makes it possible to realize ultrafast and high-precision calibration simultaneously. TOF affords the high-precision of the calibration and FSM with a high-speed clock offers the ultra-fast search. A 2.8G-3.5GHz Fractional-N PLL incorporating the proposed calibration technique is implemented in 55nm CMOS process. The measured calibration time for a 5-bit capacitor bank is 90ns for a frequency resolution of 203KHz. Such small calibration time significantly reduces the effects of calibration time on the total lock time of the PLL.

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Section: Closed-loop Afc Technique Based On Vctrl Monitoringmentioning

confidence: 99%

An ultra-fast and high-precision VCO frequency calibration technique for fractional-N frequency synthesizers

Liu

Gan

2020

IEICE Electron. Express

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“…The second AFC technique is the relative period comparison technique [84,85] , as illustrated in Fig. 13(b).…”

Section: Fast Settling Techniquesmentioning

confidence: 99%

“…According to Ref. [84], this technique can achieve a very short AFC time (several μs or even sub-μs). But this work is not suitable for fractional-N PLL because its divider output period is not fixed but modulated by the DSM.…”

Section: Fast Settling Techniquesmentioning

confidence: 99%

CMOS analog and mixed-signal phase-locked loops: An overview

Zhang¹

2020

J. Semicond.

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CMOS analog and mixed-signal phase-locked loops (PLL) are widely used in varies of the system-on-chips (SoC) as the clock generator or frequency synthesizer. This paper presents an overview of the AMS-PLL, including: 1) a brief introduction of the basics of the charge-pump based PLL, which is the most widely used AMS-PLL architecture due to its simplicity and robustness; 2) a summary of the design issues of the basic CPPLL architecture; 3) a systematic introduction of the techniques for the performance enhancement of the CPPLL; 4) a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter (< 100 fs) with lower power consumption compared with the CPPLL, including the injection-locked PLL (ILPLL), sub-sampling (SSPLL) and sampling PLL (SPLL); 5) a discussion about the consideration of the AMS-PLL architecture selection, which could help designers meet their performance requirements.

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“…As for VCO calibration techniques, there have been some strategies presented so far [2, 3]. The period comparison method based on the time-to-voltage conversion [4] or the PFD-based edge comparison [5] work very fast, but they are complicated in structure and show speed-resolution limitations. Frequency counter-based linear search method is easy to implement but takes prohibitively long time, thus are not suitable for applications requiring fast channel switching capability.…”

Section: Introductionmentioning

confidence: 99%

Calibration Techniques for Low-Power Wireless Multiband Transceiver

Yin

Cui

Liu

et al. 2013

International Journal of Distributed Sensor Networks

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The low-power wireless transceiver is the basic silicon building block of wireless sensor networks and the internet of things. In this paper, two digital calibration and compensation techniques for low-power wireless multiband transceiver are presented to adjust the VCO's tuning curves in the frequency synthesizer and eliminate the DC offset voltage in the intermediate frequency (IF) pathway. The fuzzy binary search method is applied to VCO calibration, and gain-based DC offset cancellation (DCOC) is applied. Based on these proposed methods, a multiband transceiver is designed and fabricated in 0.18 m CMOS with 1.8 V voltage supply. Experimental results show that with 24 MHz system clock, frequency synthesizer calibration can be completed within 450 without requiring any additional calibration prescaler, achieving a calibration resolution of 1 MHz; DC offset voltage can be reduced to less than 3.5 mV for 0 to 60 dB gain, with each calibration process taking only 1.28 ms time. The proposed techniques and corresponding circuits are proved to be cost-efficient while maintaining high performance, which is suitable for multiband and multimode transceiver integration.

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A 480-MHz to 1-GHz sub-picosecond clock generator with a fast and accurate automatic frequency calibration in 0.13-µm CMOS

Cited by 12 publications

References 9 publications

An ultra-fast and high-precision VCO frequency calibration technique for fractional-N frequency synthesizers

An ultra-fast and high-precision VCO frequency calibration technique for fractional-N frequency synthesizers

CMOS analog and mixed-signal phase-locked loops: An overview

Calibration Techniques for Low-Power Wireless Multiband Transceiver

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