A 48-node All-to-all Connected Coupled Ring Oscillator Ising Solver Chip

Abstract

This paper presents a physics-based Ising solver chip fabricated in a standard 1.2V, 65 nanometer complementary metal oxide semiconductor (CMOS) technology featuring an all-to-all architecture with 48 spins and a highly-uniform coupling circuit with integer weights ranging from -14 to +14. Existing locally-connected architectures suffer from size and digital computation overheads while embedding an arbitrary graph. In contrast, our all-to-all connected design allows any graph with up to 48 nodes to be directly mapped to the hardware. The key idea of the all-to-all architecture is to strongly couple a horizontal oscillator with a vertical oscillator so that each horizontal-vertical oscillator pair intersects with all other pairs in the cross-bar style array. The multi-bit coupling circuit was realized by cascading 1-bit coupler stages comprising a pair of inverters and two transmission gates. Statistical measurements were carried out on the fabricated Ising solver chips for different problem sizes, graph densities, operating temperatures, problem instances, and solution samples. The measured oscillation period, power consumption, and relaxation time for different problems are also reported. Finally, we show that dynamically merged spins can achieve higher weight resolution without hardware changes.

Oscillatory neural network learning for pattern recognition: an on-chip learning perspective and implementation

“…ONNs with their phase dynamics are intrinsically analog in nature and implemented with analog computing for low-power implementations (Delacour et al, 2023a ). However, digital ONNs are attractive implementations for studying various applications, fast demonstration, and investigating scalability (Moy et al, 2022 ; Lo et al, 2023 ). In particular, a digital ONN implementation on FPGA was introduced in Abernot et al ( 2021 ) to explore novel ONN architectures, learning algorithms, and applications.…”