A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

Howard, Jason D.; Dighe, Saurabh; Vangal, Sriram; Ruhl, G.; Borkar, Nitin; Jain, Shailendra; Erraguntla, Vasantha; Konow, Michael; Riepen, Michael; Gries, Matthias; Droege, Guido; Lund-Larsen, Tor; Steibl, Sebastian; Borkar, S.; De, Vivek; Wijngaart, Rob Van der

doi:10.1109/jssc.2010.2079450

Cited by 334 publications

(161 citation statements)

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“…Howard et al [10] described an evolutionary approach for a fine-grained power management of multi-core NoC using Voltage and Frequency Islands (VFI). The power management protocols in the software exploit the benefits of the VFI through the DVFS.…”

Section: Evolution Of Dvfsmentioning

confidence: 99%

A comparative study of voltage/frequency scaling in NoC

Usman

Khan

2013

IEEE International Conference on Electro-Information Technology , EIT 2013

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Abstract-Voltage and frequency is dynamically scaled to produce energy efficient multi-core networkon-chip (NoC). A detailed analysis of the techniques employed for this purpose are studied and based on the optimized performance the most effective ones are reported. We also highlight the most promising high performance and energy minimizing techniques.Index Terms-Network-on-chip, dynamic voltage and frequency scaling, leakage power

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Section: Evolution Of Dvfsmentioning

confidence: 99%

A comparative study of voltage/frequency scaling in NoC

Usman

Khan

2013

IEEE International Conference on Electro-Information Technology , EIT 2013

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“…The low complexity 2D mesh has been used by most fabricated many-core systems including RAW [5], AsAP [6], TILE64 [7], AsAP2 [8] and Intel 48-core Single-Chip Cloud Computer (SCC) [9].…”

Section: Related Workmentioning

confidence: 99%

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

Xiao

Baas

2013

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

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Abstract. Network-on-Chips (NoCs) are used to connect large numbers of processors in many-core processor architecture because they perform better than less scalable methods such as global shared buses. Among all NoC design parameters, NoC topologies define how nodes are placed and connected and greatly affect the performance, energy efficiency, and circuit area of many-core processor arrays. Due to its simplicity and the fact that processor tiles are traditionally square or rectangular, 2D mesh is mostly used for existing on-chip networks. However, efficiently mapping applications can be a challenge for cases that require communication between processors that are not adjacent on the 2D mesh. Motivated by the fact that applications often have largely localized communication patterns, we have proposed an 8-neighbor mesh topology and a 6-neighbor topology with hexagonal-shaped processor tiles, both of which increase local connectivity while keep much of the simplicity of a mesh-based topology. We have physically designed a 16-bit DSP processor and the corresponding processor arrays which utilize all three topologies. A 1080p H.264/AVC residual video encoder and a 54 Mbps 802.11a/11g OFDM wireless LAN baseband receiver are mapped onto all topologies. The 6-neighbor hexagonal grid topology incurs a 2.9% area increase per tile compared to the 4-neighbor 2D mesh, but its much more effective interprocessor interconnect yields an average total application area reduction of 21%, an average power reduction of 17%, and a total application interprocessor communication distance reduction of 19%.

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“…Each tile (shaded in grey) contains two P54c cores, with 16KB of L1 instruction and data cache, 256KB of L2 cache per core, special on-chip memory known as the message passing buffer (MPB), and a router. The MPB on each tile is 16KB, for a total of 384KB of on-chip memory on the SCC [1]. There are four memory controllers that the SCC uses to access off-chip memory.…”

Section: A Intel Sccmentioning

confidence: 99%

“…Recently, core counts have numbered in the dozens [1]- [3] and we are rapidly approaching systems with hundreds of cores on a single die. For example, the SingleChip Cloud Computer (SCC) experimental processor [1] is a 48-core 'concept vehicle' created by Intel Labs as a platform for many-core software research. Systems such as this allow researchers to explore application development and better understand hardware and software bottlenecks that could impact the performance of future many-core systems.…”

Section: Introductionmentioning

confidence: 99%

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Performance analysis of broadcasting algorithms on the Intel Single-Chip Cloud Computer

Matienzo

Jerger

2013

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Abstract-Efficient broadcasting is essential for good performance on distributed or multiprocessor systems. Broadcasts are commonly used to implement message passing synchronization primitives, such as barriers, and also appear frequently in the set up stage of scientific applications. The Intel Single-Chip Cloud Computer (SCC), an experimental processor, uses synchronous message passing to facilitate communication between its 48 cores. RCCE, the SCC's message passing library, implements broadcasting in a traditional way: sending n−1 unicast messages, where n is the number of cores participating in the broadcast. This implementation can hinder performance as the number of cores participating in the broadcast increases and if the data being sent to each core is large. Also in the RCCE implementation, the broadcasting core is blocked from doing any useful work until all cores receive the broadcast. This paper explores several broadcasting schemes that take advantage of the resources of the SCC and the RCCE library. For example, we explore a scheme that propagates a broadcast to multiple cores in parallel and a scheme that parallelizes offchip memory accesses which would otherwise need to be done sequentially. Our best broadcast scheme achieves a 35× speedup over the RCCE implementation. We also demonstrate that our improved broadcasting substantially reduces the time spent on communication in some benchmarks. While the broadcast schemes presented in this paper are implemented specifically for the SCC, they provide insight into the more general problem of broadcast communication and could be adapted to other types of distributed and multiprocessor systems.

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A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

Cited by 334 publications

References 5 publications

A comparative study of voltage/frequency scaling in NoC

A comparative study of voltage/frequency scaling in NoC

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

Performance analysis of broadcasting algorithms on the Intel Single-Chip Cloud Computer

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