A 48-860MHz digital cable tuner IC with integrated RF and IF selectivity

Abstract

A single-chip wide-band tuner with an active splitter for cable data modems and set-top boxes is realized in a 0.5µm, 30GHz BiCMOS technology [1]. The IC employs a single down-conversion, low-IF architecture and can receive signals in the 48-860MHz frequency range. Fully integrated selectivity is obtained in combination with a channel decoder. Power consumption is 1.5W with a 3.3V supply.Existing dual-conversion architectures like [2-4], remove the need for tuner alignment, but still use external fixed frequency filters. The goal of this work is to fully integrate the TV front-end selectivity and make external RF and filter components (like coils, SAW and ceramic filters) obsolete, without compromising performance.The IC (Fig. 25.3.1) contains a splitter amplifier, RF AGC amplifier, switchable RF band-pass filter, RF polyphase filter, double quadrature down-conversion mixer, IF polyphase filter, groupdelay correction filter, low-pass filter, IF AGC amplifier, fully integrated voltage controlled oscillator (VCO), synthesizer and a received signal strength indication (RSSI) circuit.

Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting

“…The mixer's gain mismatch can be minimized by using a proper architecture like passive mixer and good layout techniques, but the LO phase imbalance is usually over 1 degree even with sophisticated calibration, which implies that no more than 40 dB image rejection can be achieved. Therefore, to achieve over 60 dB image rejection ratio, double-quadrature architecture, which can relax the matching requirement of the LO, is preferred [6,7]. As shown in Figure 2(b), the double-quadrature architecture handles the down-conversion with complex LO and complex RF signals.…”

“…The design of this programmable filter is still an issue. The doublequadrature down-converter provides inherited 3rd harmonic distortion suppression [6], and the programmable bandpass filter removes those 5 LO + IF interferences and achieves 5th harmonic component suppression as well. In addition, the programmable filter can also serve as rough band selection and relax linearity challenges of the following stages.…”

“…to 806 MHz; these specifications can be achieved if a multistage passive polyphase filter is used [6][7][8]14]. The schematic of a broadband generator is shown in Figure 7(a); the differential RF signals are applied at nodes in1 (and in2) and in3 (and in4), respectively.…”

“…The double-quadrautre architecture relaxes the matching requirement for the RF and LO inputs; however, the matching requirement for the mixer remains in the range of 0.1%, which is still quite challenging. Passive CMOS switching mixer is chosen because it has better tradeoff between matching and power consumption [6,8]; large-size transistors are used to improve the matching of the mixer section while power consumption is not affected. High swing LO is used to have high over-drive voltage, which also decreases the noise contribution of the switches.…”

“…A divide-by-2 circuit is used to generate accurate quadrature LO signals. The main building blocks of the PLL such as VCO are similar to those reported in [6,10], and hence they are not further discussed. In order to enable functionality test even without the onchip PLL, an external LO also can be applied for tuner frontend.…”