A 477mW NoC-based digital baseband for MIMO 4G SDR

Clermidy, Fabien; Bernard, Christian; Lemaire, R.; Martin, Jérôme; Miro-Panades, Ivan; Thonnart, Yvain; Vivet, Pascal; Wehn, Norbert

doi:10.1109/isscc.2010.5433920

Cited by 73 publications

(40 citation statements)

References 5 publications

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“…In addition to FPGAs, complete NoC-based SoC ASICs are presented in [7,17,72] together with a post-layout evaluation. However, neither of the works evaluate the scalability and instead focus on a single design point.…”

Section: Functional Scalabilitymentioning

confidence: 99%

A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

Hansson

Goossens

2011

Des Autom Embed Syst

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A growing number of applications are integrated on the same System on Chip in the form of hardware and software Intellectual Property (IP). Many applications have firm or soft real-time requirements and require bounds on latency and throughput. To accommodate the growing number of application requirements, the on-chip interconnect must offer scalability on the physical, architectural and functional level.Networks on Chip (NoC) are proposed as a scalable communication architecture that is also able to deliver guaranteed performance. Traditionally, NoCs focus on delivering physical and architectural scalability. The functional scalability, i.e. the ability to satisfy an increasing number of increasingly demanding requirements with a constant cost/performance ratio, is often overlooked. The onus is on the interconnect design flow that translates user requirements to an interconnect instance. While mature tooling exists for many of the IPs, interconnect design flows are an active research area, with few concrete examples, and few large-scale case studies.As the main contribution of this work, we demonstrate a complete operational interconnect design flow for multiple real-time applications, and quantitatively evaluate the functional scalability on two large-scale industrial case studies. We illustrate the steps of the flow, going from requirement specification all the way to simulation of synthesised netlists in a 90 nm and 65 nm low-power standard-cell technology. We show that the interconnect and design flow offer scalability, on the physical, architectural as well as the functional level.

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Section: Functional Scalabilitymentioning

confidence: 99%

A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

Hansson

Goossens

2011

Des Autom Embed Syst

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“…The scheme is applied to MAGALI [12], which is a baseband chip consisting of 23 cores connected by an asynchronous NoC, each core having its own clock generator. MAGALI is intended to quickly switch between different Quality-of-Service (QoS) modes which correspond to a telecommunication standard.…”

Section: Application To Power Optimization Of Real-time Systemsmentioning

confidence: 99%

Sustainability through massively integrated computing: Are we ready to break the energy efficiency wall for single-chip platforms?

Pande¹,

Clermidy²,

Puschini³

et al. 2011

2011 Design, Automation &Amp; Test in Europe

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-While traditional cluster computers are more constrained by power and cooling costs for solving extreme-scale (or exascale) problems, the continuing progress and integration levels in silicon technologies make possible complete end-user systems on a single chip. This massive level of integration makes modern multicore chips all pervasive in domains ranging from climate forecasting and astronomical data analysis, to consumer electronics, smart phones, and biological applications. Consequently, designing multicore chips for exascale computing while using the embedded systems design principles looks like a promising alternative to traditional clusterbased solutions. This paper aims to present an overview of new, farreaching design methodologies and run-time optimization techniques that can help breaking the energy efficiency wall in massively integrated single-chip computing platforms.

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“…Local and cellular wireless communication throughputs are expected to increase to hundreds of Mbps and even beyond 1 Gbps [1][2][3]. With this increased growth for bandwidth comes larger systems integration complexity and higher energy consumption per packet.…”

Section: Introductionmentioning

confidence: 99%

LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

Shirani-Mehr

Baas

2013

VLSI Design

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An energy efficient low-density parity-check (LDPC) decoder using an adaptive wordwidth datapath is presented. The decoder switches between a Normal Mode and a reduced wordwidth Low Power Mode. Signal toggling is reduced as variable node processing inputs change in fewer bits. The duration of time that the decoder stays in a given mode is optimized for power and BER requirements and the received SNR. The paper explores different Low Power Mode algorithms to reduce the wordwidth and their implementations. Analysis of the BER performance and power consumption from fixed-point numerical and post-layout power simulations, respectively, is presented for a full parallel 10GBASE-T LDPC decoder in 65 nm CMOS. A 5.10 mm 2 low power decoder implementation achieves 85.7 Gbps while operating at 185 MHz and dissipates 16.4 pJ/bit at 1.3 V with early termination. At 0.6 V the decoder throughput is 9.3 Gbps (greater than 6.4 Gbps required for 10GBASE-T) while dissipating an average power of 31 mW. This is 4.6× lower than the state of the art reported power with an SNR loss of 0.35 dB at BER = 10 −7 .

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A 477mW NoC-based digital baseband for MIMO 4G SDR

Cited by 73 publications

References 5 publications

A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

Sustainability through massively integrated computing: Are we ready to break the energy efficiency wall for single-chip platforms?

LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

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