A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance

Bowman, Keith; Tschanz, James; Lu, Shih-Lien; Aseron, Paolo; Khellah, Muhammad; Raychowdhury, Arijit; Geuskens, Bibiche; Tokunaga, Carlos; Wilkerson, Chris; Karnik, Tanay; De, Vivek

doi:10.1109/jssc.2010.2089657

Cited by 227 publications

(168 citation statements)

References 17 publications

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“…This eliminates errors caused by the errant instruction. A similar technique is multi-reissue [8] (Fig. 3(b)).…”

Section: The Proposed Tedpimentioning

confidence: 99%

“…Razor-Lite register [5] is applied to detect errors, and multi-reissue [8] is utilized to correct errors that escape software. The signoff frequency of CK802 in SMIC 40ll after routing is 70 MHz.…”

Section: Quantitative Analysis 421 Experimental Setupmentioning

confidence: 99%

“…The in-situ error detection and correction (EDAC) techniques [4,5,6,7,8,9,10,11,12,13] are proposed to eliminate the timing margins. They monitor timing violations by specially designed circuits, and then take measures to recover functionality of the design if such a violation occurs.…”

Section: Introductionmentioning

confidence: 99%

“…They monitor timing violations by specially designed circuits, and then take measures to recover functionality of the design if such a violation occurs. Examples of EDAC techniques include Razor [3,4,5,9], TIMBER [14], TDTB [6], DSTB [6,8], time borrowing [10,12,14], and etc. These techniques either correct timing errors with large cycle penalty, which in return degrades energy efficiency and throughput [10,15]; or require massive hardware cost and high design complexity to reduce the penalty, which makes them unsuitable for commercial processors [16].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Light-weight one-cycle timing error correction based on hardware software co-design

Ding

Yan

et al. 2016

IEICE Electron. Express

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A light-weight one-cycle EDAC (timing error detection and correction) technique is proposed to eliminate timing margins resulting from process, voltage, temperature and aging (PVTA) variations. The collaborative approach applies TEDPI (timing error deletion programming interface) to pre-detect most of the errors through an offline error prediction model, and pre-correct them at compilation time by using a specially designed error avoidance instruction. Experimental results based on a three-stage commercial processor show that TEDPI has improved peak performance of the traditional EDAC system by 15.6% and reduced the energy consumption by 4.4% with less than 0.71% area overhead.

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“…This eliminates errors caused by the errant instruction. A similar technique is multi-reissue [8] (Fig. 3(b)).…”

Section: The Proposed Tedpimentioning

confidence: 99%

Section: Quantitative Analysis 421 Experimental Setupmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Light-weight one-cycle timing error correction based on hardware software co-design

Ding

Yan

et al. 2016

IEICE Electron. Express

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show abstract

“…However, the currently used DVS methods cannot decrease the supply voltage to the best, because sufficient timing and voltage margins are reserved to resist the impact of environmental variations, transistor model inaccuracy, and EDA tool limitation, etc. [1,2,3,4,5,6].…”

Section: Introductionmentioning

confidence: 99%

An improved timing monitor for deep dynamic voltage scaling system

Shan

et al. 2013

IEICE Electron. Express

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In the current Dynamic voltage scaling (DVS) integrated circuits, sufficient timing and voltage margins are typically wasted, because it is difficult to anticipate the exact amount by which the voltage or frequency should be scaled. The on-chip timing monitoring method is effective for this problem. In this paper, an improved timing monitor circuit with a fast error comparator is designed to detect and correct timing errors, and then it is used in a DVS system on 65 nm CMOS technology for deep DVS. Post-layout simulation results show that the monitor performs well in different process corners with a wide voltage range and wide temperature range. Compared with the non-DVS circuit supplied by a fixed 1.2 V voltage, our timing monitor based DVS system can save, on average, 33.4% dynamic power in different corners at the expense of 22.9% increased area.

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Process Variation Challenges and Solutions Approaches

Onabajo

Silva-Martínez

2012

Analog Circuit Design for Process Variation-Resilient Systems-on-a-Chip

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A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance

Cited by 227 publications

References 17 publications

Light-weight one-cycle timing error correction based on hardware software co-design

Light-weight one-cycle timing error correction based on hardware software co-design

An improved timing monitor for deep dynamic voltage scaling system

Process Variation Challenges and Solutions Approaches

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