A 446.6K-gates 0.55&amp;#x2013;1.2V H.265/HEVC decoder for next generation video applications

Tsai, Chang-Hung; Wang, Hsiuan-Ting; Liu, Chia‐Lin; Li, Yao; Lee, Chen‐Yi

doi:10.1109/asscc.2013.6691043

Cited by 10 publications

(11 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The decoding throughput achieved by this work reaches up to 1920 × 1080 with 52 fps under a 250MHz working frequency. Compared with other works, normalized performance of this work is 6.3×, 7.43× and 1.33× that of the two GPP-based schemes ( [14] and [15]) and one ASIC scheme [16], respectively.…”

Section: Normalized Performance =mentioning

confidence: 65%

An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform

Liu

Wang

Chen

et al. 2016

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYThis paper presents the design of a multiple-standard 1080 high definition (HD) video decoder on a mixed-grained reconfigurable computing platform integrating coarse-grained reconfigurable processing units (RPUs) and FPGAs. The proposed RPU, including 16 × 16 multi-functional processing elements (PEs), is used to accelerate computeintensive tasks in the video decoding. A soft-core-based microprocessor array is implemented on the FPGA and adopted to speed-up the dynamic reconfiguration of the RPU. Furthermore, a mail-box-based communication scheme is utilized to improve the communication efficiency between RPUs and FPGAs. By exploiting dynamic reconfiguration of the RPUs and static reconfiguration of the FPGAs, the proposed platform achieves scalable performances and cost trade-offs to support a variety of video coding standards, including MPEG-2, AVS, H.264, and HEVC. The measured results show that the proposed platform can support H.264 1080 HD video streams at up to 57 frames per second (fps) and HEVC 1080 HD video streams at up to 52fps under 250MHz, at the same time, it achieves a 3.6× performance gain over an industrial coarse-grained reconfigurable processor for H.264 decoding, and a 6.43× performance boosts over a general purpose processor based implementation for HEVC decoding.

show abstract

Section: Normalized Performance =mentioning

confidence: 65%

An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform

Liu

Wang

Chen

et al. 2016

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

show abstract

“…To meet the above requirements, several decoder designs have been recently proposed [4]- [6]. An FPGA prototype has been proposed in [4] to decode 1080p@60fps with a 7-stage pipeline architecture.…”

Section: )mentioning

confidence: 99%

“…Although this approach unified the control flow, the pipeline buffer size was still based on 64x64 for the worst-case condition. Furthermore, [6] proposed a 1080p@30fps decoder that used a four-stage pipeline with embedded compression to reduce bandwidth. Several single module designs have also been proposed [7]- [14].…”

Section: )mentioning

confidence: 99%

A QFHD 30-frames/s HEVC Decoder Design

Chiang

Ting

Chen

et al. 2016

IEEE Trans. Circuits Syst. Video Technol.

View full text Add to dashboard Cite

The HEVC video standard provides superior compression with large and variable-sized coding units and advanced prediction modes, which leads to high buffer costs, memory bandwidth and irregular computation for ultra high definition (HD) video decoding hardware. Thus, this paper presents an HEVC decoder with a four-stage mixed block size pipeline to reduce by approximately 91% the pipeline stage buffer size compared with the 64x64 block-based pipeline. The high memory bandwidth due to motion compensation problem was solved by 16x16 blockbased data access, precision-based data access and a smart buffer to reduce the data bandwidth by 88%. In addition, for irregular computation, a reconfigurable architecture was adopted to unify the variable size transform. A common intra prediction module was also designed with a 4x4 block-based bottom up computation for variable size intra prediction and modes in a regular manner. Furthermore, the corner position computation for the motion vector predictor (MVP) was applied to handle variable size motion compensation. Finally, the implementation with the TSMC 90 nm CMOS process used 467 K logic gates and 15.778 KBytes of on-chip memory and supported 4096×2160@30fps video decoding at a 270 MHz operation frequency. Index Terms-High efficiency video coding, decoder, VLSI implementationI.

show abstract

“…Huang et al [9] presents a complete HM 4.0 compliant H.265/MPEG-HEVC decoder for 4K video applications, which is based on a pure hardwired architecture implemented using 40 nm CMOS silicon technology, while consuming 76 mW for the decoder core only. Tsai et al [10] presents a 1080p30 capable 90 nm ASIC implementation of a HEVC decoder operating at 188 MHz. Besides this publication single functional units are described in the literature [11]- [18].…”

Section: Related Workmentioning

confidence: 99%

FPGA implementation of a full HD real-time HEVC main profile decoder

Engelhardt

Moller

Hahlbeck

et al. 2014

IEEE Trans. Consumer Electron.

View full text Add to dashboard Cite

High Efficiency Video Coding (HEVC) is the newest video coding standard approved by the ISO/IEC and ITU-T in January 2013. By providing a video coding efficiency gain up to 50 % compared to H. 264/MPEG-4 AVC high profile, the complexity of the used algorithms has raised significantly. Targeting video formats with higher spatial and temporal resolutions - e.g. 4Kp60 in broadcast applications make implementing encoders and decoders a challenging task. A few software based implementations on DSPs and general purpose CPUs are known from the literature which suffer from real-time constraints, power dissipation and hardware costs of these systems. In this paper a pure hardware implementation of a Main Profile H. 265/MPEG-HEVC Full HD capable decoder is presented solving both real-time and power constraints respectively. As a first implementation approach a state-of-the-art FPGA technology is chosen as a prototyping platform. This design can be used as a starting point for an ASIC implementation(1)

show abstract

A 446.6K-gates 0.55–1.2V H.265/HEVC decoder for next generation video applications

Cited by 10 publications

References 6 publications

An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform

An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform

A QFHD 30-frames/s HEVC Decoder Design

FPGA implementation of a full HD real-time HEVC main profile decoder

Contact Info

Product

Resources

About