A 43μwatt 3-bit Flash ADC designed with TMCC and Bit Referenced Encoder in 180nm CMOS Technology

Abstract

The analog-to-digital converter (ADC) is an essential part of system-on-chip (SoC) products because it bridges the gap between the analog physical world and the digital logical world. In the digital domain, low power and low voltage requirements are becoming more important issues as the channel length of MOSFET shrinks below 0.25 sub-micron values. Moreover, SoC trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design. Thus, this thesis is to investigate high speed, low power, and low voltage CMOS flash ADCs for SoC applications. In this paper an area efficient low power high Speed 3-bit Flash Type ADC using bit referenced encoder is proposed in 180 nm CMOS technology. The concept of Threshold Modified Comparator Circuit (TMCC) is also introduced as a modification of the conventional comparator. The proposed design of the ADC occupies an active area of 0.0036 mm2 and consumes 43.146 μW of Average Power while operating with an input frequency (fin) of 10 MHz and a supply voltage of 1.8 Volt.