A 40GOPS 250mW massively parallel processor based on matrix architecture

Nakajima, M.; Noda, Haruhiko; Dosaka, K.; Kiyoshi, Nakata; Higashida, M.; Yamamoto, Osamu; Mizumoto, K.; Kondo, Hiroyuki; Shimazu, Y.; Arimoto, Kazutami; Saitoh, Katsuya; Shimizu, Toshihisa

doi:10.1109/isscc.2006.1696216

Cited by 48 publications

(23 citation statements)

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“…We have developed a massive parallel processor based on a SRAM-embedded matrix architecture [11]- [15], [20], [21], which overcomes the limitations in parallelism of previous architectures. This massive-parallel SIMD matrix architecture achieves for example 40 GOPS performance for 16-bit additions at 200 MHz clock frequency and 250 mW power dissipation in a 90 nm CMOS technology [11].…”

Section: Massive-parallel Memory-embedded Simd Matrix Architecturementioning

confidence: 99%

“…This massive-parallel SIMD matrix architecture achieves for example 40 GOPS performance for 16-bit additions at 200 MHz clock frequency and 250 mW power dissipation in a 90 nm CMOS technology [11]. It is furthermore programmable for all processing functions required for multimedia VLSI chips.…”

Section: Massive-parallel Memory-embedded Simd Matrix Architecturementioning

confidence: 99%

“…5, the plain text of the block-cipher algorithm is normally represented in two-dimensional array format [24], because conventional processors are limited to a singleaccess data width, such as 16 or 32 bit. On the other hand, the proposed SIMD matrix processing module has a flexible data width architecture up to 256 or 512 bits [11], [16]. The massive-parallel memory-embedded SIMD matrix can therefore adopt one-dimensional line format to take advantage of its highly parallelism.…”

Section: Efficient Aes Processing With Simd Matrix Processormentioning

confidence: 99%

“…The massive-parallel memory-embedded SIMD matrix has been proposed as a novel SIMD multimedia processor, which provides a better way for processing several types of multimedia applications [11]- [16]. It achieves highly parallel processing with low power consumption, and can thus target the mobile product applications.…”

Section: Introductionmentioning

confidence: 99%

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Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems

Kumaki

Koide

Mattausch

et al. 2011

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper presents a software-based parallel cryptographic solution with a massive-parallel memory-embedded SIMD matrix (MTX) for data-storage systems. MTX can have up to 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. Furthermore, a next-generation SIMD matrix called MX-2 has been developed by expanding processing-element capability of MTX from 2-bit to 4-bit processing. These SIMD matrix architectures are verified to be a better alternative for processing repeated-arithmetic and logical-operations in multimedia applications with low power consumption. Moreover, we have proposed combining Content Addressable Memory (CAM) technology with the massive-parallel memory-embedded SIMD matrix architecture to enable fast pipelined table-lookup coding. Since both arithmetic logical operation and table-lookup coding execute extremely fast on these architectures, efficient execution of encryption and decryption algorithms can be realized. Evaluation results of the CAMless and CAM-enhanced massive-parallel SIMD matrix processor for the example of the Advanced Encryption Standard (AES), which is a widelyused cryptographic algorithm, show that a throughput of up to 2.19 Gbps becomes possible. This means that several standard data-storage transfer specifications, such as SD, CF (Compact Flash), USB (Universal Serial Bus) and SATA (Serial Advanced Technology Attachment) can be covered. Consequently, the massive-parallel SIMD matrix architecture is very suitable for private information protection in several data-storage media. A further advantage of the software based solution is the flexible update possibility of the implemented-cryptographic algorithm to a safer future algorithm. The massive-parallel memory-embedded SIMD matrix architecture (MTX and MX-2) is therefore a promising solution for integrated realization of real-time cryptographic algorithms with low power dissipation and small Si-area consumption. key words: matrix-processing architecture, SIMD, bit-serial and wordparallel, CAM, table-lookup coding, cryptographic algorithm, AES

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Section: Massive-parallel Memory-embedded Simd Matrix Architecturementioning

confidence: 99%

Section: Massive-parallel Memory-embedded Simd Matrix Architecturementioning

confidence: 99%

Section: Efficient Aes Processing With Simd Matrix Processormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems

Kumaki

Koide

Mattausch

et al. 2011

IEICE Trans. Inf. & Syst.

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“…Figure 12 shows the chip photograph of a matrix processor [12]. This processor has 32 sub-circuit blocks called "banks" each of which consists of 64 2-bit processing elements and 128 512-bit SRAMs.…”

Section: Evaluation Using An Applicationmentioning

confidence: 99%

Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme

Shirahama

Mizutani

Natsui

et al. 2010

IEICE Trans. Inf. & Syst.

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Hirokatsu SHIRAHAMA†a) , Takashi MATSUURA †b) , Student Members, Masanori NATSUI †c) , and Takahiro HANYU †d) , Members SUMMARYA multiple-valued current-mode (MVCM) circuit using current-flow control is proposed for a power-greedy sequential linear-array system. Whenever operation is completed in processing element (PE) at the present stage, every possible current source in the PE at the previous stage is cut off, which greatly reduces the wasted power dissipation due to steady current flows during standby states. The completion of the operation can be easily detected using "operation monitor" that observes input and output signals at latches, and that generates control signal immediately at the time completed. Since the wires of data and control signals are shared in the proposed MVCM circuit, no additional wires are required for currentflow control. In fact, it is demonstrated that the power consumption of the MVCM circuit using the proposed method is reduced to 53 percent in comparison with that without current-source control.

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Secure data processing with massive‐parallel SIMD matrix for embedded SoC in digital‐convergence mobile devices

Kumaki

Koide

Fujino

2016

IEEJ Transactions Elec Engng

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This paper presents secure data processing with a massive-parallel single-instruction multiple-data (SIMD) matrix for embedded system-on-chip (SoC) in digital-convergence mobile devices. Recent mobile devices are required to use private-informationsecure technology, such as cipher processing, to prevent the leakage of personal information. However, this adds to the device's required specifications, especially cipher implementation for fast processing, power consumption, low hardware cost, adaptability, and end-user's operation for maintaining the safety condition. To satisfy these security-related requirements, we propose the interleaved-bitslice processing method, which combines two processing concepts (bitslice processing and interleaved processing), for novel parallel block cipher processing with five confidentiality modes on mobile processors. Furthermore, we adopt a massiveparallel SIMD matrix processor (MX-1) for interleaved-bitslice processing to verify the effectiveness of parallel block cipher implementation. As the implementation target from the Federal Information Processing Standardization-approved block ciphers, a data encryption standard (DES), triple-DES, and Advanced Encryption Standard (AES) algorithms are selected. For the AES algorithm, which is mainly studied in this paper, the MX-1 implementation has up to 93% fewer clock cycles per byte than other conventional mobile processors. Additionally, the MX-1 results are almost constant for all confidentiality modes. The practical-use energy efficiency of parallel block cipher processing with the evaluation board for MX-1 was found to be about 4.8 times higher than that of a BeagleBoard-xM, which is a single-board computer and uses the ARM Cortex-A8 mobile processor. Furthermore, to improve the operation of a single-bit logical function, we propose the development of a multi-bit logical library for interleaved-bitslice cipher processing with MX-1. Thus, the number of clock cycles is the smallest among those reported in other related-studies. Consequently, interleaved-bitslice block cipher processing with five confidentiality modes on MX-1 is effective for the implementation of parallel block cipher processing for several digital-convergence mobile devices.

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A 40GOPS 250mW massively parallel processor based on matrix architecture

Cited by 48 publications

References 1 publication

Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems

Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems

Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme

Secure data processing with massive‐parallel SIMD matrix for embedded SoC in digital‐convergence mobile devices

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