A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process

Shirahama, M.; Agata, Y.; Kawasaki, Takeshi; Nishihara, R.; Abe, W.; Kuroda, Naoki; Sadakata, H.; Uchikoba, T.; Takahashi, Kunimasa; Egashira, K.; Honda, Shigeto; Miura, Miho; Hashimoto, Shoushin; Kikukawa, H.; Yamauchi, Hiroyuki

doi:10.1109/jssc.2005.845995

IEEE J. Solid-State Circuits

2005

DOI: 10.1109/jssc.2005.845995

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A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process

M. Shirahama¹,

Y. Agata²,

Takeshi Kawasaki³

et al.

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A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process

Cited by 1 publication

References 6 publications

Ultra-Low Voltage Nano-Scale DRAM Cells

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