A 40 nm 16-Core 128-Thread SPARC SoC Processor

Optimal Unate Decomposition Method for Synthesis of Mixed CMOS VLSI Circuits

“…Step 8: Including states 11, 14 to TS which belong to x 2 variable, form conflict pairs (3)(4)(5)(6)(7)(8)(9)(10)(11)(6)(7)(8)(9)(10)(11)(12)(13)(14) for the already existing negative influence pairs of x 3 . This violates the unateness of the current US.…”

“…This is posing increasing demands for devices operating at low power and high speed [5], [6]. With custom made chips coming into focus, the designers are pushing more and more functionalities on a single chip [7], [8], [9]. In fact, designers are now pushing billions of transistors in a single chip [10].…”

Full System Simulation of Optically Interconnected Chip Multiprocessors Using gem5

“…These nodes then send as many messages as they have buffered (both cache block and control messages) up to the maximum which can fit within the slot, thus using the full data bandwidth available. Current high performance shared memory servers use an electronic crossbar for on-chip interconnect [7], but area and power consumption does not scale well with increased number of cores. To compare with the optical TDM network, we use electronic mesh networks (Figure 1b), which have been widely proposed for larger core counts, e.g.…”

An FPGA implementation for a high-speed optical link with a PCIe interface

“…The standardization and wide use of PCIe are important: they suggest that the design described in this thesis can easily be integrated in various configurations since the link between the interface and the computing node only consists of the standard PCIe 2.0 interconnect. For example, PCIe 2.0 is integrated in the recent fourth generation UltraSPARC T3 SoC processor [28]. In fact, the PCI standard's transparency to the implemented PCI software has been an important element influencing its wide-scale adoption in industry.…”