A −40 dB EVM, 77 MHz Dual-Band Tunable Gain Sub-Sampling Receiver Front End in 65-nm CMOS

Kale, Ajinkya; Popuri, Suchendranath; Koeberle, Michael; Sturm, Johannes; Pasupureddi, Vijaya Sankara Rao

doi:10.1109/tcsi.2018.2878342

Cited by 16 publications

(13 citation statements)

References 29 publications

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“…In general, a single path switch-capacitor mixer serves the purpose of down-conversion [13]. The traditional single-path sub-sampling mixer is shown in Fig.…”

Section: A Single Path Sub-sampling Mixermentioning

confidence: 99%

“…Additionally, they do not suffer from the disadvantages such as DC offset, second-order non-linearity and 1/f noise due to non-zero IF. There are few sub-sampling architectures are reported, including low-power sub-sampling architecture [8]- [11], multi-standard RF receiver with two subsampling mixer stages [12] [13]. However, there is no subsampling mixer-first receiver architecture reported till date due to the inherent disadvantages of sub-sampling leading to noise folding led to high noise figure and lack of impedance matching at the RF port due to non-zero IF.…”

Section: Introductionmentioning

confidence: 99%

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A Process Scalable Architecture for Low Noise Figure Sub-Sampling Mixer-First RF Front-End

Rena

Verma

Pasupureddi

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Sub-sampling down-conversion mixers have not been considered as a mixer-first RF front-ends due to their disadvantages of high noise figure and lack of impedance matching at the RF port, even though they offer the advantages of less complex clocking circuits and low-power consumption. In this work, a process scalable architecture for low noise figure impedance matched sub-sampling mixer-first RF front-end is proposed addressing the issues of noise folding and impedance matching with process scalable circuit components like switches, capacitors and inverters. A scheme to reject the selected IF odd-harmonics of fs/4 by multi-path sampling is proposed, alleviating the effect of noise folding and leading to low noise figure sub-sampling mixer-first RF front-end. The combination of the complex impedance band-pass filter along with the IF-LNA provide the tuned impedance matching. In addition, analysis on sub-sampling frequency plan, amount of harmonic rejection and its effect on noise figure, transparency of the impedance at the RF port and its tunability with respect to the input impedance of IF-LNA is presented. To validate the analysis and modeling, as well as to explain the architecture, an example low-power narrow-band IoT(NB-IoT) standard RF front-end is realized in 1.2 V, 65 nm CMOS and it is observed that the performance predicted by analytical equations is in agreement with Spectre RF simulations.

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“…In general, a single path switch-capacitor mixer serves the purpose of down-conversion [13]. The traditional single-path sub-sampling mixer is shown in Fig.…”

Section: A Single Path Sub-sampling Mixermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Process Scalable Architecture for Low Noise Figure Sub-Sampling Mixer-First RF Front-End

Rena

Verma

Pasupureddi

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Dual-band non-contiguous CA has been performed with two separate reconfigurable RF front-ends [5], but reducing the component count further usually requires complex multiband devices, such as low noise amplifiers (LNA) and filters [6]- [9]. Alternatively, novel downconversion techniques such as using six-port correlators, harmonic recombination, or subsampling downconverters have been investigated [10]- [12].…”

Section: Introductionmentioning

confidence: 99%

Concurrent Multiband Direct RF Sampling Receivers

Henthorn

O’Farrell

Anbiyaei

et al. 2023

IEEE Trans. Wireless Commun.

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Direct radio frequency (RF) sampling receivers are investigated for use in concurrent multiband reception for mobile broadband (MBB) applications. The recent proliferation of different frequency bands and standards in wireless communications has allowed large increases in mobility and throughput, but the number of receivers in a device is limited by physical space and power consumption. Software Defined Radio (SDR) is increasingly being explored to reduce the number of analog RF components required. This paper examines the use of direct RF digitization, allowing tunable and concurrent reception of multiple bands with a single RF front-end. Full mathematical models of both Nyquist and subband sampling receivers are presented and used to investigate a quadband LTE receiver, which is modeled in Simulink and implemented in a hardware-in-theloop (HWIL) testbed. Individual bands are simulated to have at worst -95dBm sensitivity for 16-QAM with Nyquist sampling and -83dBm with subband sampling. Desensitization of the receivers due to multiband processing is evaluated theoretically and experimentally, showing a maximum of 3dB degradation, which is within the LTE standard for adjacent band interference.

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“…In addition, in nuclear instruments and biomedical imaging applications, multiphase delayed clocks are used for the development of the multichannel analog‐to‐digital converters (ADCs) and/or time‐to‐digital converters (TDCs). In wireless LAN baseband design, the multiphase clocks are used in frequency translation technique, to lower the sampling rate requirements for ADC…”

Section: Introductionmentioning

confidence: 99%

Charge controlled delay element enabled widely linear power efficient MPCG‐MDLL in 1.2V, 65nm CMOS

Kammari

Pasupureddi

2019

Circuit Theory & Apps

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Summary In this work, a robust, low‐power, widely linear multiphase clock generation and multiplying delay‐locked loop (MPCG‐MDLL) architecture is realized, using a new differential charge‐mode delay element circuit topology. The heart of any MPCG‐MDLL architecture is the delay element, and hence, the characteristics of the delay element influence the overall performance of the MPCG‐MDLL, in terms of its specifications such as peak‐to‐peak jitter, lock range, delay range, control voltage range, and power consumption. The proposed eight‐phase MPCG‐MDLL along with the charge‐mode delay element outperforms the conventional MPCG‐MDLLs that deploy delay elements such as a current‐starved inverter (CSI), wide‐range CSI, triply controlled delay cell, digital‐controlled delay element, and the like. The eight‐phase MPCG‐MDLL along with the new charge‐mode delay element circuit topology is implemented in 1.2‐V, 65‐nm CMOS technology. The performance results show that the eight‐stage delay line has a delay range from 640 to 960 ps over the rail‐to‐rail control voltage range. The implemented MPCG‐DLL is robust over process, voltage, and temperature (PVT) corners and exhibits a lock range of 400 MHz and a peak‐to‐peak jitter of less than 60 fs for all the DLL output phases and peak‐to‐peak jitter of 0.54 and 1.24 ps for the synthesized 5‐GHz clocks for an input reference clock frequency of 1.25 GHz. The MPCG‐MDLL consumes 4.74 mW of power and occupies an area of 0.017 mm2.

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A −40 dB EVM, 77 MHz Dual-Band Tunable Gain Sub-Sampling Receiver Front End in 65-nm CMOS

Cited by 16 publications

References 29 publications

A Process Scalable Architecture for Low Noise Figure Sub-Sampling Mixer-First RF Front-End

A Process Scalable Architecture for Low Noise Figure Sub-Sampling Mixer-First RF Front-End

Concurrent Multiband Direct RF Sampling Receivers

Charge controlled delay element enabled widely linear power efficient MPCG‐MDLL in 1.2V, 65nm CMOS

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