A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor

McIntyre, H.; Wendell, D.; Kai, Lin; Kaushik, P.; Seshadri, S.; Wang, A.; Sundararaman, Vijayaraghavan; Wang, Ping; Kim, Song; Hsu, W.-J.; Park, Heechoul; Levinsky, G.; Lu, J.; Chirania, M.; Heald, R.; Lazar, P.; Dharmasena, S.

doi:10.1109/jssc.2004.838017

Cited by 9 publications

(5 citation statements)

References 3 publications

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“…From the data table spatial correlation is better compared to local variables, under process variation. In order to validate the data 65 nm 16 MB Intel Xeon L3 cache (Chang et al, 2007) and a 90 nm 4 MB sun Sparc L2 cache (McIntyre et al, 2005) is compared and computes a floating point arithmetic instruction for each cycle is executed. Further the clock latency is also found.…”

Section: Approach Related To C/c++ /Cacti and Hdlmentioning

confidence: 99%

Optimization of Clock Tree Synthesis Under Stochastic Process Variation Modeling for Multi-Fpga Systems

Sampath¹

2013

American Journal of Applied Sciences

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In this age of scientific computing, the experiment models and evaluation is a commonly employed rendition of the simulation methods. In addition to the optimality, the methods which depict underlying uncertainty in process variation. It is accomplished by adjusting number of samples on delay and wire width. Here addresses the thermal profile, if temperature gradually increases, also reduce worst case clock skew under thermal variation. Under the SSTA analysis the mean delay is 6.2 to 5.2% and standard deviation from 7.5 to 7.6% is reduced. Therefore the overall performance measure in storage and the run time is very low. Extensive simulation studies show that of how does one accurately and efficiently postprocess stochastic simulation fields and how does one effectively and succinctly convey the results.

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Section: Approach Related To C/c++ /Cacti and Hdlmentioning

confidence: 99%

Optimization of Clock Tree Synthesis Under Stochastic Process Variation Modeling for Multi-Fpga Systems

Sampath¹

2013

American Journal of Applied Sciences

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“…In order to validate the SRAM modeling of CACTI-D, we compare its projections against published data of a 65nm 16MB Intel Xeon L3 cache [8] and a 90nm 4MB Sun SPARC L2 cache [22]. We choose input specifications for the caches and device/interconnect assumptions based on the published data.…”

Section: Validationmentioning

confidence: 99%

A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

Thoziyoor

Ahn

Monchiero

et al. 2008

2008 International Symposium on Computer Architecture

171

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In this paper we introduce CACTI-D, a significant enhancement of CACTI 5.0. CACTI-D adds support for modeling of commodity DRAM technology and support for main memory DRAM chip organization. CACTI-D enables modeling of the complete memory hierarchy with consistent models all the way from SRAM based L1 caches through main memory DRAMs on DIMMs.We illustrate the potential applicability of CACTI-D in the design and analysis of future memory hierarchies by carrying out a last level cache study for a multicore multithreaded architecture at the 32nm technology node. In this study we use CACTI-D to model all components of the memory hierarchy including L1, L2, last level SRAM, logicprocess based DRAM or commodity DRAM L3 caches, and main memory DRAM chips. We carry out architectural simulation using benchmarks with large data sets and present results of their execution time, breakdown of power in the memory hierarchy, and system energy-delay product for the different system configurations. We find that commodity DRAM technology is most attractive for stacked last level caches, with significantly lower energy-delay products.

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“…(5) (6) , the constraint function for columns, can be constructed in a similar way. The global constraint function is the product of the Boolean-AND operations between and .…”

Section: B the Second Stage Of The Pageb Algorithmmentioning

confidence: 99%

“…The Power4, Power4+, and Power5 include respectively 1.41 MB, 1.5 MB, and 1.875 MB of on-die L2 caches [5]. The 64-bit 1.6-GHz SPARC processor contains 4 MB of on-die L2 cache [6]. The 1.5-GHz Itanium 2 processor has 6 MB of on-die L3 (level three) cache [7].…”

Section: Introductionmentioning

confidence: 99%

An Efficient Algorithm for Spare Allocation Problems

Lin¹,

Yeh

Kuo

2006

IEEE Trans. Rel.

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The spare allocation problem in redundant RAM is to replace faulty rows/columns of memory cells with spare rows/columns. To solve the problem, comparison-based search tree structures were used in traditional exact algorithms. These algorithms are not efficient for large problems because significant amounts of data have to be retained and copied in order to generate new partial solutions. Many data may need to be compared for the removal of each redundant partial solution. To overcome these drawbacks, an efficient algorithm is proposed in this paper. The algorithm transforms a spare allocation problem into Boolean functions, and the renowned BDD is used to manipulate them. Experimental results indicate that the proposed algorithm is very efficient in terms of speed and memory requirements. It may also be useful for problems which can be modeled as constraint bipartite vertex cover problems.

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A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor

Cited by 9 publications

References 3 publications

Optimization of Clock Tree Synthesis Under Stochastic Process Variation Modeling for Multi-Fpga Systems

Optimization of Clock Tree Synthesis Under Stochastic Process Variation Modeling for Multi-Fpga Systems

A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

An Efficient Algorithm for Spare Allocation Problems

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