A 4‐bit ultra‐wideband complementary metal‐oxide‐semiconductor attenuator with low root‐mean‐square amplitude error

Abstract

This article presents the 4-bit ultra-wideband complementary metal-oxidesemiconductor (CMOS) attenuator in a standard 0.18-μm CMOS process. This design adopts switched bridge-T type topologies for each attenuation bit. Based on insertion losses and input P 1-dB considerations, the circuit performances can be optimized by the proper bit ordering arrangement. Therefore, the bit ordering 0.5-4-2-1 dB is employed in the 4-bit attenuator. Moreover, series inductors are added between each bit to further improve the input and output return losses. Measured results demonstrate that the attenuation range of the circuit is 7.5 dB with 0.5 dB step and the root-mean-square (RMS) amplitude error is between 0.11 and 0.13 dB from 3.1 to 10.8 GHz. The differences between simulated and measured RMS amplitude errors are less than 0.2 dB, which demonstrates the good agreement and feasibility of the design concept. The measured input P 1-dB is 15 dBm at 5 GHz and the chip area is 1.12 mm 2 including all testing pads. K E Y W O R D Sattenuator, CMOS, RMS amplitude error, ultra-wideband

Design and analysis of variable attenuator with simultaneous minimized flat amplitude error and insertion phase variations

“…Different configurations of digital attenuator are presented in the literature, including distributed, switchedpath, and switched pi/T-type. [12][13][14][15][16][17][18] Digital attenuators have relatively low insertion phase variations; however, these attenuators still suffer from drawbacks of relatively high flat amplitude error and potential limit of fine amplitude control in wideband applications because of the parasitic effect of the MOS switch. Moreover, simultaneous minimization of flat amplitude error and insertion phase variation of variable attenuators are challenging.…”

“…Digital attenuators can provide the 2 N ‐1 attenuation level with respect to reference mode by controlling N‐bit control voltage. Different configurations of digital attenuator are presented in the literature, including distributed, switched‐path, and switched pi/T‐type 12‐18 . Digital attenuators have relatively low insertion phase variations; however, these attenuators still suffer from drawbacks of relatively high flat amplitude error and potential limit of fine amplitude control in wideband applications because of the parasitic effect of the MOS switch.…”

A DC to 25 GHz 6‐bit digital attenuator based on 0.18 μm SiGe BiCMOS technology

“…4 The internal switched π/T step attenuator has merit of large attenuation range, relatively low attenuation error, and compact size. 5,6 In addition, recent studies have proposed some techniques to reduce phase variation and insertion loss. [7][8][9][10][11][12][13] For example, the attenuator adopts the first-order low-pass filter as a compensation network in parallel with the π/T type attenuator cell, which allows low phase error over a relatively wide band.…”

“…However, the switches also induce excessive insertion loss and chip size 4 . The internal switched π/T step attenuator has merit of large attenuation range, relatively low attenuation error, and compact size 5,6 . In addition, recent studies have proposed some techniques to reduce phase variation and insertion loss 7‐13 .…”