A 4&amp;#x00D7; 25-to-28Gb/s 4.9mW/Gb/s &amp;#x2212;9.7dBm high-sensitivity optical receiver based on 65nm CMOS for board-to-board interconnects

Tokuda, Takashi; Yamashita, Hiroyuki; Yazaki, Toru; Chujo, Norio; Lee, Yong; Matsuoka, Y.

doi:10.1109/isscc.2013.6487662

Cited by 24 publications

(13 citation statements)

References 2 publications

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“…(4), the gain at the low frequency can be designed by the parameter g mC and R L by considering ω is 0. The degradation characteristics of the gain at the high frequency depend on C p , R L , and T from (8) and (9). The emphasized characteristics depend on f c3 .…”

Section: Design Methodsmentioning

confidence: 96%

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A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS

Tanaka¹,

Kishine²,

Tsuchiya³

et al. 2016

IEIE Transactions on Smart Processing and Computing

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Optical communication systems are rapidly spread following increases in data traffic. In this work, a 32-Gb/s inductorless output buffer circuit with adjustable pre-emphasis is proposed. The proposed circuit consists of an output buffer circuit and an emphasis circuit. The emphasis circuit emphasizes the high frequency components and adds the characteristics of the output buffer circuit. We proposed a design method using a small-signal equivalent-circuit model and designed the compensation characteristics with a 65-nm CMOS process in detail using HSPICE simulation. We also realized adjustable emphasis characteristics by controlling the voltage. To confirm the advantages of the proposed circuit and the design method, we fabricated an output buffer IC with adjustable pre-emphasis. We measured the jitter and eye height with a 32-Gb/s input using the IC. Measurement results of double-emphasis showed that the jitter was 14% lower, and the eye height was 59% larger than single-emphasis, indicating that our proposed configuration can be applied to the design of an output buffer circuit for higher operation speed.

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Section: Design Methodsmentioning

confidence: 96%

“…Signal degradation is a key issue with high speed communication circuits. With this issue, peaking techniques are used in a high-speed communication circuit for compensation [6][7][8][9][10]. The peaking circuit realizes compensation characteristics by emphasizing the highfrequency component.…”

Section: Introductionmentioning

confidence: 99%

A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS

Tanaka¹,

Kishine²,

Tsuchiya³

et al. 2016

IEIE Transactions on Smart Processing and Computing

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“…It is very common to extend the BW of CMOS TIA with passive planar peaking inductors, as it was done in [2], [7], [8], [9], [11], [12], [13] and [14]. These components require on the other hand an enormous chip area in comparison to the entire active circuit.…”

Section: B Bandwidth Enhancementmentioning

confidence: 99%

An inductor-less ultra-compact transimpedance amplifier for 30 Gbps in 28 nm CMOS with high energy-efficiency

Szilágyi

Henker

Ellinger

2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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A transimpedace amplifier (TIA) for optical links with data rate (DR) of up to 30 Gbps is presented. The design uses several bandwidth and gain enhancement techniques such as regulated common-gate, transimpedance boosting by current injection, transimpedance/transadmittance feedback and active inductor. The design is realized in a 28 nm CMOS technology. Since the circuit does not use any passive planar inductor or other special radio frequency component the area is only 0.4 × 10 -3 mm 2 and is to our knowledge the smallest TIA reported to date in the 30 Gbps DR range. The measured bandwidth is 22 GHz with a power consumption of only 2 mW resulting in an energy efficiency of 0.067 pJ/bit. The gain of the TIA is approximately 43 dBΩ with only one stage. The TIA is suitable to be integrated into complex CMOS VLSI systems as an alternative to copper-based short-distance interconnects. An output buffer for 50 Ω matching was added to the output, allowing the measurement.

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“…In practice, a quad 25-Gb/s per channel is a possible solution for the purpose [2][3]. Yet, efforts have been conducted to increase the bandwidth further and also to decrease power consumption simultaneously.…”

Section: Introductionmentioning

confidence: 99%

A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology

Kim

et al. 2014

2014 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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A 50-Gb/s differential transimpedance amplifier is realized in a standard 65nm CMOS process, which exploits asymmetric transformer peaking technique for bandwidth extension and employs a modified regulated-cascode input stage with a shunt-feedback common-source amplifier for differential signaling. Measured results demonstrate 52-dB transimpedance gain, 50-GHz bandwidth for 50fF photodiode capacitance, -12.3dBm sensitivity for 10 -12 BER, and 49.2-mW power dissipation from a single 1.2-V supply. To the best of authors' knowledge, this chip achieves the fastest operation speed among the recently reported gigabit CMOS transimpedance amplifiers. The chip occupies the total area of 1.2×0.8mm 2 including pad.

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A 4× 25-to-28Gb/s 4.9mW/Gb/s −9.7dBm high-sensitivity optical receiver based on 65nm CMOS for board-to-board interconnects

Cited by 24 publications

References 2 publications

A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS

A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS

An inductor-less ultra-compact transimpedance amplifier for 30 Gbps in 28 nm CMOS with high energy-efficiency

A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology

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