A 4.92-5.845 GHz direct-conversion CMOS transceiver for IEEE 802.11a wireless LAN

Behzad, Arya; Lin, Eric W.; Carter, K.; Kappes, Martin; Shi, Zhan; Lin, Li; Wu, S.; Anand, S.; Nguyen, Trung‐Kien; Yuan, D.; Wong, Y.C.; Fong, V.; Yeung, B.; Rofougaran, A.

doi:10.1109/rfic.2004.1320614

Cited by 4 publications

(4 citation statements)

References 6 publications

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“…Previous linearity improvement techniques for CMOS, described in [6] and [7], were only for single-ended topology, which is not appropriate for SOC because of its bad common-mode noise rejection. Also, differential circuit linearity improvement techniques, described 0018-9200/$20.00 © 2006 IEEE in [8] and [9] are for a pseudo-differential amplifier-based circuit. This is also weak for common-mode noise disturbances which will be discussed later.…”

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confidence: 99%

A 13-dB IIP3 Improved Low-Power CMOS RF Programmable Gain Amplifier Using Differential Circuit Transconductance Linearization for Various Terrestrial Mobile D-TV Applications

Kim¹,

Kim²

2006

IEEE J. Solid-State Circuits

103

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A CMOS RF digitally programmable gain amplifier (RF PGA), covering various terrestrial mobile digital TV standards (DMB, ISDB-T, and DVB-H) is implemented as a part of a low-IF tuner IC using 0.18-m CMOS technology. An improvement of 13-dB IIP3 is attained without significant degradation of other performance criteria like gain, noise figure, common-mode rejection ratio, etc., at similar power consumption. This is achieved by applying a newly proposed differential circuit gm (the second derivatives of transconductance) cancellation technique, called the differential multiple gated transistor (DMGTR). In the DMGTR amplifier, the negative value of gm in the fully differential amplifier can be compensated by the positive value of gm in the pseudo differential amplifier which is properly sized and biased. By adopting the DMGTR, a low-power highly linear RF PGA is implemented. Also, in order to have wide gain range with fine step resolution, a new RF PGA architecture is proposed. The measurement results of the proposed RF PGA exhibit 50-dB gain range with 0.25-dB resolution, 4.5-dB noise figure, a 4-dBm IIP3 (maximum 30 dBm) and 25-dB gain at 16-mW power consumption.

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A 13-dB IIP3 Improved Low-Power CMOS RF Programmable Gain Amplifier Using Differential Circuit Transconductance Linearization for Various Terrestrial Mobile D-TV Applications

Kim¹,

Kim²

2006

IEEE J. Solid-State Circuits

103

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“…The transceiver occupies 6mm 2 die area while consuming at most 182mW. Compared to previously published dual-band RF transceivers [1][2][3], this transceiver covers all bands specified for WLAN while achieving 50-70% smaller die area with 24-60% less power consumption.In the past, several radio architectures have been used to realize the RF transceiver [1][2][3][4]. Although two-step zero-IF architecture [1,2] decreases the LO frequency by separating the up/down conversions into two successive steps, this scheme doubles the number of mixers, LO drivers, and frequency synthesizers.…”

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confidence: 99%

“…In the past, several radio architectures have been used to realize the RF transceiver [1][2][3][4]. Although two-step zero-IF architecture [1,2] decreases the LO frequency by separating the up/down conversions into two successive steps, this scheme doubles the number of mixers, LO drivers, and frequency synthesizers.…”

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confidence: 99%

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A compact dual-band direct-conversion CMOS transceiver for 802.11a/b/g WLAN

Xu¹,

Jiang²,

Wu³

et al.

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.

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Over the past several years, the WLAN market has shown more than double digit growth, dominated mostly by network interface cards and mini-PCI solutions. More recently, WLAN is beginning to penetrate into the embedded market, including applications in home entertainment, cellular phones, PDAs, and gaming. These embedded applications place stringent constraints on cost and power consumption. In this paper, a compact fully integrated 0.18µm RF CMOS transceiver is presented that meets the IEEE 802.11a/b/g WLAN requirements and covers both the 2.4-2.4835GHz and the 4.9-5.875GHz bands. The transceiver occupies 6mm 2 die area while consuming at most 182mW. Compared to previously published dual-band RF transceivers [1][2][3], this transceiver covers all bands specified for WLAN while achieving 50-70% smaller die area with 24-60% less power consumption.In the past, several radio architectures have been used to realize the RF transceiver [1][2][3][4]. Although two-step zero-IF architecture [1,2] decreases the LO frequency by separating the up/down conversions into two successive steps, this scheme doubles the number of mixers, LO drivers, and frequency synthesizers. Therefore, it is difficult to use this architecture for low-power, small-die-area implementations. In contrast, direct-conversion radio architecture requires only one LO to achieve up/down conversion in one step and therefore, leads to a more compact and low-power design. Thus, the dual-band transceiver is implemented based on the direct-conversion architecture as shown in Fig. 5.4.1. To overcome the well-known impairments due to LO leakage and DC offset, an LO calibration loop and a successively switched DC offset cancellation loop have been implemented in the transceiver. The LO calibration loop reduces the amount of LO leakage to less than -29dBc while the successively switched DC offset cancellation loop improves the cancellation and has a shorter convergence time, which is critical for the 802.11a/g modes.The transmitter shown in Fig. 5.4.1 includes separate up-conversion mixers and class AB pre-amplifiers for the 5GHz and the 2.4GHz bands, but shares a 5 th -order LPF that has a variable gain with 14dB tuning range. Because of device mismatches, LO leakage exists in the transmitter output, which in the worst case could be only 15dB lower than the desired signal. To reduce the LO leakage, an on-chip LO leakage calibration circuit as shown in Fig. 5.4.2 is implemented in the transmitter to guarantee at least -29dBc LO leakage with at most ±3dBc change on the image tone.The transmitter delivers 2.5dBm/1dBm output power with 20dBm/23dBm OIP3 for 2.4GHz/5GHz band while meeting the ACPR requirements for 802.11a/g with EVM of -31dB/-32dB. The output power flatness across 4.9GHz~5.8GHz is 4.5dB and with a variation of 3.5dB when temperature changes from 0 to 85 0 C. The TX output power can be further increased to 8.5dBm/6dBm for the 2.4GHz/5GHz band with the same power consumption but with a higher EVM of -28dB/-29dB.The receiver shown in Fig. 5.4.1 consists of ...

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