A 4.75-64 Gb/s PAM-4 Wireline Transmitter with 3-tap FFE in 28-nm CMOS

Chen, Junkun; Gu, Youzhi; Xu, Miaomiao; Chen, Yongzhen; Wang, Cuixia; Wu, Jiangfeng

doi:10.1109/iscas46773.2023.10181487

2023 IEEE International Symposium on Circuits and Systems (ISCAS) 2023

DOI: 10.1109/iscas46773.2023.10181487

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A 4.75-64 Gb/s PAM-4 Wireline Transmitter with 3-tap FFE in 28-nm CMOS

Junkun Chen

Youzhi Gu

Miaomiao Xu

et al.

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41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology

Zhan,

Li,

Zou

et al. 2023

Electronics

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A high-speed, high-depth pre-interleaver in the proposed symbol pre-interleaving Bit MUX (PBM) was implemented to mitigate decision feedback equalizer (DFE) error propagation in a 400 G Ethernet Serializer–Deserializer (SerDes) interface. Based on the SerDes interface link architecture with 5-tap DFE, the performance of the PBM under DFE error propagation was simulated theoretically, which could obtain an interleaving gain of 0.35 dB. In the pre-interleaver, in order to significantly increase the transmission rate while keeping the larger interleaving depth, characteristic polynomial parallelization with the logic expansion method and register-based memory with interleaving technology were adopted. Finally, the pre-interleaver was fabricated with 65 nm CMOS technology, with a total area of 0.615 mm2, including the I/O pad. The measurement results show that the horizontal opening degree of the output signal can reach 0.925 UI at the data rate of 41.6 Gb/s. The total power consumption is 38.52 mW at the supply voltage of 1.2 V and frequency of 1.3 GHz.

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41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology

Zhan,

Li,

Zou

et al. 2023

Electronics

View full text Add to dashboard Cite

show abstract

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A 4.75-64 Gb/s PAM-4 Wireline Transmitter with 3-tap FFE in 28-nm CMOS

Cited by 1 publication

References 8 publications

41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology

41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology

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