A 4.5ns 256K CMOS SRAM with tri-level word line

Shinohara, Hirofumi; Anami, Keiko; Ichinose, K.; Wada, T.; Kohno, Y.; Kawai, Y.; Akasaka, Y.; Kayano, S.

doi:10.1109/isscc.1985.1156744

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A 4.5ns 256K CMOS SRAM with tri-level word line

Cited by 9 publications

References 3 publications

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