A 4.5mW digital baseband receiver for level-A evolved EDGE

2013 IEEE International Conference on Acoustics, Speech and Signal Processing

Burg

et al. 2013

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Modern wireless communication systems require efficient channel equalizer implementations. This paper explores the design space of reduced-state sequence estimation (RSSE). We show how the concept of pre-computation can be applied to greatly reduce computational complexity, such that efficient RSSE architectures can be derived. As a proof of concept, an RSSE was implemented in dedicated hardware, that achieves a 1.6 times higher hardware efficiency when compared to prior art.

Section: Vlsi Architecturementioning

confidence: 85%

Section: Introductionmentioning

confidence: 99%

Efficient vlsi implementation of reduced-state sequence estimation for wireless communications

Zwicky

2013 IEEE International Conference on Acoustics, Speech and Signal Processing

Burg

et al. 2013

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“…L = 1, can lead to significantly lower P D . The notch filter approach shows poor performance compared to the other two approaches, since the attenuation of the notch filter is not strong enough to provide an unambiguous ratio of input and output power as decision metric 3 . The PVD algorithm's detection probability is the best for SNR regimes above 4 dB, but decays rapidly below 4 dB.…”

Section: A Performance and Complexity Comparisonmentioning

confidence: 98%

“…Directly afterwards, our FOE realization computes a new f o value, as can be seen in the blue curve. An arbitrarily chosen number of time instances later (20 in this case, for the sake of clarity), an oscillator tuning word is sent from computer #2 to the RF transceiver, in order to tune the DCXO according to the frequency offset 6 Note that we have developed other critical signal-processing blocks for the GSM/EGPRS2 baseband (cf [3]), that can be mapped to our receiver testbed. estimation f o .…”

Section: Hardware Implementationmentioning

confidence: 99%

“…The detection of higher order modulation EGPRS2 signals at acceptable SNR-levels requires high-end RF transceiver ICs with very low noise figure [2], and sophisticated channel equalization and demodulation algorithms in the digital baseband [3]. In legacy GSM modes with GMSK modulation the dramatic improvement of receiver sensitivity allows the operation at low SNR-levels, e.g., [2] with an input signal power level of -110 dBm which translates to an SNR of about 7 dB 1 .…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Low-complexity frequency synchronization for GSM systems: Algorithms and implementation

Kroll

Zwicky

2012 IV International Congress on Ultra Modern Telecommunications and Control Systems

et al. 2012

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Abstract-Carrier frequency synchronization of a mobile station (MS) is a crucial task at the beginning of the cell selection procedure and during normal operation. Constant monitoring of the base-stations surrounding the MS requires robust synchronization concepts with low computational complexity. In the GSM standard, periodically transmitted frequency correction bursts (FB) provide the necessary information for synchronization. This paper presents a combined low-complexity approach for FB detection and carrier frequency estimation, which achieves high detection probability and frequency estimation accuracy. A thorough performance assessment on a GSM/EGPRS2 testbed proves the suitability of the corresponding FPGA hardware implementation.

On the Mapping of Incremental Redundancy into a Physical Layer ASIC

Weber

Kroll

et al. 2014

J Sign Process Syst

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Incremental Redundancy (IR) was introduced in GSM/EDGE and later adopted in Evolved EDGE in order to keep the throughput at an acceptable level. Legacy 2G networks with their ubiquitous coverage are apt to provide a fallback solution for the latest LTE networks. On the other hand, they provide a reliable data link for emerging M2M or IoT applications. IR data processing and controlling is specified in several layers of the GSM/EDGE protocol stack. In many state-of-the-art designs this leads to decentralized data processing, and thus to costly data movements between memories and hardware accelerators. This is prohibitive for emerging M2M designs, which demand lowest possible hardware resources. In this work, IR is implemented as part of a dedicated hardware baseband signal processing unit in order to unburden higher layer processing units from IR, reduce area, power consumption, and costs. The open source baseband framework MatPHY is extended for packet switched operation to facilitate the development of efficient IR hardware architectures. With the design parameters obtained from performance evaluations computed with MatPHY an IR architecture in a 130 nm CMOS technology B. Weber ( ) •