A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS

Reutemann, R.; Ruegg, Michael; Keyser, Fran; Bergkvist, John; Dreps, Daniel; Toifl, Thomas; Schmatz, M.

doi:10.1109/jssc.2010.2077350

Cited by 33 publications

(9 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Finally, the background CDR mode is activated in step 4 for continuous tracking of bit and byte alignment. Then, the local CDRs are turned off for most of the time to reduce power consumption and periodically turned on to track phase drift due to voltage and temperature variations, which is similar to the concept of the pulsed CDR [7]. Fig.…”

Section: B Rxmentioning

confidence: 99%

A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface

Lee

Kim

Park

et al. 2013

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

This brief presents an 8-bit parallel transceiver for low-power memory interface with a current-regulated voltagemode driver and a clock and data recovery performing both bit recovery and byte alignment. Sharing a current source by output drivers enables voltage swing control without any regulator circuit while holding the benefits of low-power voltage-mode driving. In the receiver, with only one phase rotator in a globally shared phase-locked loop, a narrow-range delay line in each deskewing phase recovery loop effectively performs seamless phase adjustment. The transceiver, implemented in a 90-nm CMOS, shows a data rate of 6 Gbit/s/ch with a bit error rate of 10 −12 and a power consumption of 2.8 mW/Gbit/s. Index Terms-Clock and data recoveries (CDRs), low-power links, memory interface, parallel links.

show abstract

Section: B Rxmentioning

confidence: 99%

A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface

Lee

Kim

Park

et al. 2013

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

show abstract

“…The link was specifically designed for this type of application and consists of 15 or 22 differential data lanes and 1 clock lane. The interface is designed as a source-synchronous link, which means that the bus clock and data are driven from the same source clock in the driving chip and the bus clock is used to latch the data in the receiving chip [11].…”

Section: Differential Memory Interfacementioning

confidence: 99%

Electronic packaging of the IBM System z196 enterprise-class server processor cage

Strach

Bosco²,

Köbel³

et al. 2012

IBM J. Res. & Dev.

View full text Add to dashboard Cite

In this paper, we describe the first-and second-level system packaging structure of the IBM zEnterprise A 196 (z196) enterprise-class server. The design point required a more than 50% overall increase in system performance (in millions of instructions per second) in comparison to its predecessor. This resulted in a new system design that includes, among other things, increased input/output bandwidth, more processors with higher frequencies, and increased current demand of more than 2,000 A for the six processor chips and two cache chips per multichip module. To achieve these targets, we implemented several new packaging technologies. The z196 enterprise-class server uses a new differential memory interface between the processor chips and custom-designed server memory modules. The electrical power delivery system design follows a substantially new approach using Vicor Factor Power A blocks, which results in higher packaging integration density and minimized package electrical losses. The power noise decoupling strategy was changed because of the availability of deep-trench technology on the new processor chip generation.

show abstract

“…For the ultra-high speed input signal of 100 Gbps or more, the synchronization signal still has large jitter and signal transmission and also has large latency. In the circuit design, when there is a latency difference between the clock and data path, the correlation of the clock to data sampling is weakened [2], resulting in an increase in the correlation jitter between the clock and data path, which reduces the jitter tolerance. Therefore, many studies have minimized the delay matching between clock and data through clock sampling and forwarding techniques, which in turn achieves noise filtering and jitter cancellation.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, many studies have minimized the delay matching between clock and data through clock sampling and forwarding techniques, which in turn achieves noise filtering and jitter cancellation. In [2], the receiver-side clock path uses a high-bandwidth filtered PLL to track data-related jitter and to cut off high-frequency jitter, but this method does not guarantee that the PLL output clock and data path are at the same frequency; the literature [3] uses a multiplying delay-locked loop (MDLL) to reset the oscillator jitter at the rate of the reference clock frequency, which does not require a high bandwidth loop to the suppress oscillator jitter, reducing the complexity of the design, but this can subject the MDLL to large duty cycle distortion. A region-efficient phase filtering technique is proposed in [4] to filter the jitter between cascaded repeaters, but the noise environment is not fundamentally eliminated, and the jitter accumulated by subsequent cascaded circuits degrades the system performance and jitter tolerance.…”

Section: Introductionmentioning

confidence: 99%

A Low-Latency, Low-Jitter Retimer Circuit for PCIe 6.0

et al. 2023

View full text Add to dashboard Cite

As the PCIe 6.0 specification places higher requirements on signal integrity and transmission latency, it becomes especially important to improve signal transmission performance at the physical layer of the transceiver interface. Retimer circuits are a key component of high-speed serial interfaces, and their delay and jitter size directly affect the overall performance of PCIe. For the typical retimer circuit with large-latency and low-jitter performance, this paper proposes a low-latency and low-jitter Retimer circuit based on CDR + PLL architecture for PCIe 6.0, using a jitter-canceling filter circuit to eliminate the frequency difference between the retiming clock and data, reduce the retiming clock jitter, and improve the quality of Retimer output data. The data are sampled using the retiming clock and then output, avoiding the problem of large penetration latency of typical retimer circuits. The circuit is designed using the CMOS 28 nm process. Simulation results show that when 112 Gbps PAM4 data are input to the retimer circuit, the Retimer penetration latency is 27.3 ps, which is 83.5% lower than the typical Retimer structure; the output jitter data are 741 fs, a 31.4% reduction compared to the typical retimer structure.

show abstract

A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS

Cited by 33 publications

References 5 publications

A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface

A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface

Electronic packaging of the IBM System z196 enterprise-class server processor cage

A Low-Latency, Low-Jitter Retimer Circuit for PCIe 6.0

Contact Info

Product

Resources

About