A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V $V_{\mathrm {DDmin}}$

Dong, Qing; Jeloka, Supreet; Saligane, Mehdi; Kim, Yejoong; Kawaminami, Masaru; Harada, Ayako; Miyoshi, Seiji; Yasuda, Makoto; Blaauw, David; Sylvester, Dennis

doi:10.1109/jssc.2017.2776309

Cited by 77 publications

(41 citation statements)

References 20 publications

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“…A third method is to use pulse width modulated WLs such that no two WLs are active simultaneously [28], removing the danger of data corruption, but at the cost of a 2.35x increase in periphery area. Finally, nonconventional technologies can be used, such as monolithic 3D integration [25], [26], or deeply depleted channel technology [36]. Emerging technologies present their own challenges however; for example, DDC technology demonstrates stability issues [37] and disturb risks, and results in poor performance/voltage scaling (100Mhz@0.6V.…”

Section: Avoid Data Corruption While Maintaining High Operating Frequmentioning

confidence: 99%

BLADE: An in-Cache Computing Architecture for Edge Devices

Simon

Qureshi

Rios

et al. 2020

IEEE Trans. Comput.

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Area and power constrained edge devices are increasingly utilized to perform compute intensive workloads, necessitating increasingly area and power efficient accelerators. In this context, in-SRAM computing performs hundreds of parallel operations on spatially local data common in many emerging workloads, while reducing power consumption due to data movement. However, in-SRAM computing faces many challenges, including integration into the existing architecture, arithmetic operation support, data corruption at high operating frequencies, inability to run at low voltages, and low area density. To meet these challenges, this work introduces BLADE, a BitLine Accelerator for Devices on the Edge. BLADE is an in-SRAM computing architecture that utilizes local wordline groups to perform computations at a frequency 2.8x higher than state-of-the-art in-SRAM computing architectures. BLADE is integrated into the cache hierarchy of low-voltage edge devices, and simulated and benchmarked at the transistor, architecture, and software abstraction levels. Experimental results demonstrate performance/energy gains over an equivalent NEON accelerated processor for a variety of edge device workloads, namely, cryptography (4x performance gain/6x energy reduction), video encoding (6x/2x), and convolutional neural networks (3x/1.5x), while maintaining the highest frequency/energy ratio (up to 2.2Ghz@1V) of any conventional in-SRAM computing architecture, and a low area overhead of less than 8%.

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Section: Avoid Data Corruption While Maintaining High Operating Frequmentioning

confidence: 99%

BLADE: An in-Cache Computing Architecture for Edge Devices

Simon

Qureshi

Rios

et al. 2020

IEEE Trans. Comput.

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“…DRC 2 [4] implements carry logic across BLs to facilitate complex operations. Finally, Dong et al [11] rely on deeply depleted channel technology and an unconventional 4T bitcell design to achieve an ultra-low voltage iSC architecture.…”

Section: Related Work -Bitline Computingmentioning

confidence: 99%

“…In particular, DRC 2 's architecture deviates significantly from typical cache structure as it utilizes 10T SRAM cells and complex periphery for maximum performance, resulting in what is more an accelerator than a cache. Alternatively, the ultra low voltage (0.3V) iSC architecture presented in [11] relies on unconventional CMOS technology (deeply depleted channel) and modified 4T bitcells, known to suffer from stability issues [9] and disturb risks, as well as showing poor performance with voltage scaling (100Mhz@0.6V).…”

Section: Related Work -Bitline Computingmentioning

confidence: 99%

Blade

Simon

Qureshi

Levisse

et al. 2019

Proceedings of the 2019 Great Lakes Symposium on VLSI

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The increasing ubiquity of edge devices in the consumer market, along with their ever more computationally expensive workloads, necessitate corresponding increases in computing power to support such workloads. In-memory computing is attractive in edge devices as it reuses preexisting memory elements, thus limiting area overhead. Additionally, in-SRAM Computing (iSC) efficiently performs computations on spatially local data found in a variety of emerging edge device workloads. We therefore propose, implement, and benchmark BLADE, a BitLine Accelerator for Devices on the Edge. BLADE is an iSC architecture that can perform massive SIMD-like complex operations on hundreds to thousands of operands simultaneously. We implement BLADE in 28nm CMOS and demonstrate its functionality down to 0.6V, lower than any conventional state-ofthe-art iSC architecture. We also benchmark BLADE in conjunction with a full Linux software stack in the gem5 architectural simulator, providing a robust demonstration of its performance gain in comparison to an equivalent embedded processor equipped with a NEON SIMD co-processor. We benchmark BLADE with three emerging edge device workloads, namely cryptography, high efficiency video coding, and convolutional neural networks, and demonstrate 4x, 6x, and 3x performance improvement, respectively, in comparison to a baseline CPU/NEON processor at an equivalent power budget.

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“…In a TCAM, the time to evaluate the output often called the matchline (ML) is the key factor in deciding the search speed. Typical TCAMs have 32/64/96/144-bit entry size with 128/256/512/1024 number of words [16][17][18][19]. The writing strategy and drivers in a TCAM are same as of static random access memory (SRAM) with the exception of the extra decoder to generate mask wordline signals.…”

Section: Introductionmentioning

confidence: 99%

The analogy of matchline sensing techniques for content addressable memory (CAM)

Mishra¹,

Mahendra

Hussain

et al. 2020

IET Computers & Digital Techniques

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Performance of a memory depends on the storage stability, yield and sensing speed. Differential input and the latching time of sense amplifiers are considered as primary performance factors in static random access memory. In a content addressable memory (CAM), the sensing is carried out through the matchline (ML) and the time for evaluation is the key to decide the search speed. The density of CAM is on a rise to accommodate a higher amount of information which increases the power dissipation associated with it. Issues such as the logical threshold variation and lower noise margin between match and mismatch are critical in the operation of a CAM. A good ML sensing technique can reduce the ML power with enhanced evaluation speed. This work provides an analogy of various ML sensing techniques based on their pre-charging, evaluation and performance improvement strategies. Estimation on the power dissipation and evaluation time are made and in-depth analysis on their power-speed-overhead trade-off are carried on 64-bit CAM macros.

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A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V $V_{\mathrm {DDmin}}$

Cited by 77 publications

References 20 publications

BLADE: An in-Cache Computing Architecture for Edge Devices

BLADE: An in-Cache Computing Architecture for Edge Devices

Blade

The analogy of matchline sensing techniques for content addressable memory (CAM)

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