A 3D-CMOS compatible silicon photo-sensor with a large vertical photosensitive area

Alirezaei, Iman Sabri; Vierhaus, Jörg; Burte, Edmund P.

doi:10.1007/s11082-017-0965-z

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2017

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“…In this work, the approach of 30 µm-deep trench isolation is used to increase the efficiency of pixel isolation in a 3D butt-coupled photodetector array with a vertically photoactive area as deep as 30 µm [4,5]. Here, the aforementioned methods for passivation and filling trenches could not be used efficiently.…”

Section: Introductionmentioning

confidence: 99%

Analysis of pn Junction Deep Trench Isolation with SU-8/SiO2-Liner Passivation in a Linear Butt-Coupled 3D CMOS Si Photodetector Array

Alirezaei

Vierhaus

Burte

2017

Proceedings of Eurosensors 2017, Paris, France, 3–6 September 2017

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Abstract:The realization of 30 µm-deep trench isolation in a linear array of butt-coupled 3D CMOS silicon photodetectors is investigated by implementing the formation of a shallow n + -p junction and SiO2-liner over the trench sidewalls as well as the SU-8 filling trenches for passivation. The dependency of the dark I-V curve on the trench isolation scheme is analyzed by monitoring the dynamic dark I-V measurements of four samples including the schemes of single-trench isolation with different widths and the scheme of double-trench isolation. The highest and the lowest dark currents are measured in the detectors with the widest single-trench isolation and the double-trench isolation, respectively.

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Section: Introductionmentioning

confidence: 99%