A 390ps 1000-gate array using GaAs super-buffer FET logic

Nakamura, Hiroshi; Tanaka, Kiyofumi; Tsunotani, Masanori; Kawakami, Y.; Akiyama, Masahiro; Kaminishi, Katsuzo

doi:10.1109/isscc.1985.1156810

Cited by 6 publications

(2 citation statements)

References 4 publications

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“…These improvements come at the price of increased circuit complexity, consumption and delay. The latter limitations have been solved by the super-buffered architecture (SBFL) [36][37][38], also reported in Figure 3c. In the classical buffer stage, the D-mode transistor acts as a fixed pull-down resistor, whose value should trade-off pull-down delay (requiring a small resistance value) and pull-up current consumption (requiring instead a large resistance value).…”

Section: Gaas-based Logic Gatesmentioning

confidence: 99%

GaAs-Based Serial-Input-Parallel-Output Interfaces for Microwave Core-Chips

et al. 2021

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Microwave core-chips are highly integrated MMICs that are in charge of all the beam-shaping functions of a transmit-receive module within a phased array system. Such chips include switches, amplifiers and attenuators, phase shifters, and possibly other elements, each to be controlled by external digital signals. Given the large number of control lines to be integrated in a core-chip, the embedding of a serial to parallel interface is indispensable. Digital design in compound semiconductor technology is still rather challenging due to the absence of complementary devices and the availability of a limited number of metallization layers. Moreover, in large arrays, high chip yield and repeatability are required. This paper discusses and compares challenges and solutions for the key sub-circuits of GaAs serial to parallel converters for core-chip applications, reviewing the pros and cons of the different implementations proposed in the literature.

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Section: Gaas-based Logic Gatesmentioning

confidence: 99%

GaAs-Based Serial-Input-Parallel-Output Interfaces for Microwave Core-Chips

et al. 2021

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“…By replacing the load resistors with a normally ON load transistor, DCFL and BDCFL based on E/D devices can be implemented [14]. In [18,19] the SuperBuffered FET Logic was introduced as a DCFL improvement exploiting an output buffer stage realized by Enhancement FETs. The SBFL exhibits better fan-out capability, better noise margins, and comparable rise and fall time with respect to its DCFL counterpart, against a slightly higher area occupation and DC power consumption.…”

Section: The Inverter Port Implementation Based On Bfl (A) Sdfl (B)mentioning

confidence: 99%

Design and Realization of GaAs Digital Circuit for Mixed Signal MMIC Implementation in AESA Applications

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Ciccognani

et al. 2011

International Journal of Microwave Science and Technology

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A complete design flow starting from the technological process development up to the fabrication of digital circuits is presented. The aim of this work is to demonstrate the GaAs Enhancement/Depletion (E/D) double stop-etch technology implementation feasibility for digital applications, aimed at mixed signal circuit integration. On the basis of the characterization of small E/D devices with different Gate peripheries, developed by the SELEX-SI foundry, and the analysis of several GaAs-based logical families, the most suitable logic for the available technology has been selected. Then, simple test vehicles (level shifters, NOR logic gates and D Flip-Flops) have been designed, realized, and measured to validate the design strategy applied to the GaAs E/D process. These logical circuits are preliminary to the design of a more complex serial-to-parallel converter, to be implemented onto the same chip together with RF analog blocks, such as stepped attenuators and phase shifters.

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