A 350MHz low-OSR ΔΣ current-steering DAC with active termination in 0.13μm CMOS

Clara, Martin; Klatzer, W.; Wiesbauer, A.; Straeussnigg, Dietmar

doi:10.1109/isscc.2005.1493897

Cited by 5 publications

(2 citation statements)

References 3 publications

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“…audio DACs [23]. However, there is an increasing interest in ∆Σ DACs for moderate resolution and higher bandwidth transmitters for wireless applications over the last decade [8,[24][25][26][27]. The use ∆Σ DACs in these transmitters has been driven by the concept of Software Defined Digital Radios (SDR/DR).…”

Section: ∆σ Dac Based Transmittersmentioning

confidence: 99%

“…This would allow the use of NTFs other than of the type N T F (z) = (1 − z −1 ) m used in this work. Higher in-band SNDR is possible by optimizing the location of zeroes in the NTF instead of placing them only at DC [24,25]. This leads to more "time-consuming" operations in the DSM like multiplications (or multiplication through additions) which are relatively easier to achieve at lower clock rates.…”

Section: Future Workmentioning

confidence: 99%

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Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Bhide

2015

Linköping Studies in Science and Technology. Dissertations

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Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for high-data-rate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconfiguration for multiple radio standards. ∆Σ DACs can fit very well into this trend of digital architectures as they contain a large digital signal processing component and offer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction filter order is reduced.Achieving a large bandwidth from ∆Σ DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ∆Σ DAC architectures, even in nanometer CMOS processes. Time-interleaved ∆Σ (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs.The first work is an 8-GS/s interleaved ∆Σ DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ∆Σ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, −57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to iv be limited by the testing setup for sending high-speed digital data into the prototype.The performance of a two-channel interleaved ∆Σ DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this effect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 − z −1 ) n . It is shown that a low-order FIR filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. The...

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Section: ∆σ Dac Based Transmittersmentioning

confidence: 99%

Section: Future Workmentioning

confidence: 99%

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Bhide

2015

Linköping Studies in Science and Technology. Dissertations

View full text Add to dashboard Cite

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A resistive DAC for a multi-stage sigma-delta modulator DAC with dynamic element matching

Irfansyah

Lehmann

Jenkins³

et al. 2018

Analog Integr Circ Sig Process

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Advanced Data Converters

Manganaro

2011

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Need to get up to speed quickly on the latest advances in high performance data converters? Want help choosing the best architecture for your application? With everything you need to know about the key new converter architectures, this guide is for you. It presents basic principles, circuit and system design techniques and associated trade-offs, doing away with lengthy mathematical proofs and providing intuitive descriptions upfront. Everything from time-to-digital converters to comparator-based/zero-crossing ADCs is covered and each topic is introduced with a short summary of the essential basics. Practical examples describing actual chips, along with extensive comparison between architectural or circuit options, ease architecture selection and help you cut design time and engineering risk. Trade-offs, advantages and disadvantages of each option are put into perspective with a discussion of future trends, showing where this field is heading, what is driving it and what the most important unanswered questions are.

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A 350MHz low-OSR ΔΣ current-steering DAC with active termination in 0.13μm CMOS

Cited by 5 publications

References 3 publications

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

A resistive DAC for a multi-stage sigma-delta modulator DAC with dynamic element matching

Advanced Data Converters

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