Proceedings of the IEEE 1995 Custom Integrated Circuits Conference
DOI: 10.1109/cicc.1995.518247
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A 35 Mb/s mixed-signal decision-feedback equalizer for disk-drive applications

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Cited by 9 publications
(9 citation statements)
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“…In a previous mixed-signal DFE implementation, a 10-b Up/Down (U/D) counter followed by a 6-b DAC was used to build each discrete-time integrator, as shown in Figure 3(a) [5]. The integer input is a binary signal with value ±1.…”
Section: Mixed-signal Integratormentioning
confidence: 99%
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“…In a previous mixed-signal DFE implementation, a 10-b Up/Down (U/D) counter followed by a 6-b DAC was used to build each discrete-time integrator, as shown in Figure 3(a) [5]. The integer input is a binary signal with value ±1.…”
Section: Mixed-signal Integratormentioning
confidence: 99%
“…Currentoutput multipliers form the product of the coefficient c k and the delayed binary data â[n-k]. They are implemented using switched transconductors [5]. The resulting current is converted to a voltage by a transresistance (or i2v) stage.…”
Section: Circuit Designmentioning
confidence: 99%
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