A 345 mW Heterogeneous Many-Core Processor With an Intelligent Inference Engine for Robust Object Recognition

A scalable word-parallel associative memory for smallest Euclidean distance (ED) search is presented. Due to the applied concept of distance to clock-number mapping, the reported architecture is digital in nature and scalable to advanced technology. Furthermore, the reference data of feature vectors can be scaled in principle to any vector dimension and number. Handling of the numerical complexity of the ED without large consumption of Silicon area is achieved by an area-efficient circuit, which uses the same adder for absolute-difference calculation of vector components and subsequent square calculation by sequential addition of partial products. Additionally, a clock-number minimization algorithm is proposed to significantly reduce the clock-number needed for the search when the smallest ED is a large value. The concept of the proposed architecture has been experimentally verified by measurement results from real chips fabricated in a 180 nm CMOS technology, in which the architecture is configured for parallel smallest ED search among 32 reference vectors with each vector having 16 8-bit elements. For the application example of codebook-based data compression, the fabricated test chip achieved 1.19 µs average search time, 5.77 µs worst-case search time and low power consumption of 8.75 mW at the maximum clock frequency of 47 MHz and nominal power supply voltage V dd = 1.8 V. At reduced power supply voltage V dd = 1.2 V, a smaller power consumption of 2.80 mW at an also smaller maximum clock frequency of 24 MHz is measured. In comparison to previous analog–digital architecture, a reduction of the normalized power-delay product per matching operation by about a factor 1.6 at V dd = 1.8 V (about factor 2.5 at V dd = 1.2 V) is obtained with best-case data for the analog–digital architecture and average-case data for the proposed fully-digital architecture.

Section: Introductionmentioning

confidence: 99%

Associative memory architecture for word-parallel smallest Euclidean distance search using distance mapping into clock-number domain

Akazawa¹,

Sasaki²,

Mattausch³

2014

“…In all VLSI processors reported using such algorithms, the original feature extraction process is either modified to fit the hardware implementation [5][6][7][8] or carried out only in some small regions of interest (ROIs). [9][10][11][12] Therefore, much effort is needed to maintain the image representing performance of the simplified algorithms. Furthermore, even for running the simplified feature extraction algorithms, the power consumptions of these processors are still large.…”

Section: Introductionmentioning

confidence: 99%

VLSI processor with a configurable processing element array for balanced feature extraction in high-resolution images

Zhu¹,

Shibata²

2014

A VLSI processor employing a configurable processing element array (PEA) is developed for a newly proposed balanced feature extraction algorithm. In the algorithm, the input image is divided into square regions and the number of features is determined by noise effect analysis in each region. Regions of different sizes are used according to the resolutions and contents of input images. Therefore, inside the PEA, processing elements are hierarchically grouped for feature extraction in regions of different sizes. A proof-of-concept chip is fabricated using a 0.18 µm CMOS technology with a 32 × 32 PEA. From measurement results, a speed of 7.5 kfps is achieved for feature extraction in 128 × 128 pixel regions when operating the chip at 45 MHz, and a speed of 55 fps is also achieved for feature extraction in 1920 × 1080 pixel images.

“…18) To solve this problem, many applicationspecific very large-scale integration (VLSI) processors are developed. 19,20) Such processors greatly enhance the performance of learning algorithms, making real-time performance possible. Therefore, VLSI hardware solutions not only for real-time recognition but also for real-time learning of a large number of samples are in high demand.…”

Section: Introductionmentioning

confidence: 99%

Real-Time Very Large-Scale Integration Recognition System with an On-Chip Adaptive K-Means Learning Algorithm

Hou

Zhu

et al. 2013

A very large-scale integration (VLSI) recognition system equipped with an on-chip learning capability has been developed for real-time processing applications. This system can work in two functional modes of operation: adaptive K-means learning mode and recognition mode. In the adaptive K-means learning mode, the variance ratio criterion (VRC) has been employed to evaluate the quality of K-means classification results, and the evaluation algorithm has been implemented on the chip. As a result, it has become possible for the system to autonomously determine the optimum number of clusters (K). In the recognition mode, the nearest-neighbor search algorithm is very efficiently carried out by the fully parallel architecture employed in the chip. In both modes of operation, many hardware resources are shared and the functionality is flexibly altered by the system controller designed as a finite-state machine (FSM). The chip is implemented on Altera Cyclone II FPGA with 46K logic cells. Its operating clock is 25 MHz and the processing times for adaptive learning and recognition with 256 64-dimension feature vectors are about 0.42 ms and 4 µs, respectively. Both adaptive K-means learning and recognition functions have been verified by experiments using the image data from the COIL-100 (Columbia University Object Image Library) database.