1987
DOI: 10.1109/jssc.1987.1052806
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A 34-ns 1-Mbit CMOS SRAM using triple polysilicon

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Cited by 17 publications
(1 citation statement)
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“…It is done simply by using two pairs of output transistors in parallel and delaying the switching of one pair in respect of the other [56] [57], or by precharging the output at an intermediate level, in a first phase of the switching, and after so me time the output switching is completed [58] [59]. In [60] the same technique is used but with the aim of reducing the ringing in the receiver, taking into account the distortion introduced by the transmission line that connects the output driver with the receivers in other ICs.…”
Section: Low Noise Output Driver Design Techniquesmentioning
confidence: 99%
“…It is done simply by using two pairs of output transistors in parallel and delaying the switching of one pair in respect of the other [56] [57], or by precharging the output at an intermediate level, in a first phase of the switching, and after so me time the output switching is completed [58] [59]. In [60] the same technique is used but with the aim of reducing the ringing in the receiver, taking into account the distortion introduced by the transmission line that connects the output driver with the receivers in other ICs.…”
Section: Low Noise Output Driver Design Techniquesmentioning
confidence: 99%