A 32-KB ePCM for Real-Time Data Processing in Automotive and Smart Power Applications

Pasotti, M.; Zurla, Riccardo; Carissimi, Marcella; Auricchio, C.; Brambilla, D.; Calvetti, E.; Capecchi, L.; Croce, L.; Gallinari, D.; Mazzaglia, C.; Rana, Vikas; Cabrini, A.; Torelli, G.

doi:10.1109/jssc.2018.2828805

Cited by 18 publications

(15 citation statements)

References 17 publications

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“…The chip is intended for digital storage in automotive applications. The ePCM elementary cell is based on an NMOS selector [ 21 ] and occupies 0.19 μm 2 of silicon area. A 256-KB macrocell was included in the test chip in 8 independent instances in order to increase the total number of cells in a single chip.…”

Section: Methodsmentioning

confidence: 99%

Characterization and Programming Algorithm of Phase Change Memory Cells for Analog In-Memory Computing

et al. 2021

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In this paper, a thorough characterization of phase-change memory (PCM) cells was carried out, aimed at evaluating and optimizing their performance as enabling devices for analog in-memory computing (AIMC) applications. Exploiting the features of programming pulses, we discuss strategies to reduce undesired phenomena that afflict PCM cells and are particularly harmful in analog computations, such as low-frequency noise, time drift, and cell-to-cell variability of the conductance. The test vehicle is an embedded PCM (ePCM) provided by STMicroelectronics and designed in 90-nm smart power BCD technology with a Ge-rich Ge-Sb-Te (GST) alloy for automotive applications. On the basis of the results of the characterization of a large number of cells, we propose an iterative algorithm to allow multi-level cell conductance programming, and its performances for AIMC applications are discussed. Results for a group of 512 cells programmed with four different conductance levels are presented, showing an initial conductance spread under 6%, relative current noise less than 9% in most cases, and a relative conductance drift of 15% in the worst case after 14 h from the application of the programming sequence.

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Section: Methodsmentioning

confidence: 99%

Characterization and Programming Algorithm of Phase Change Memory Cells for Analog In-Memory Computing

et al. 2021

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“…The ePCM elementary cell, sketched in Fig. 1, is based on an NMOS selector and occupies 0.19 μm 2 of silicon area [11]. A PCM evaluation board has been employed and customized to allow the configuration of current pulses applied to cells.…”

Section: A Test Vehicle and Evaluation Boardmentioning

confidence: 99%

Phase-change memory cells characterization in an analog in-memory computing perspective

Antolini

Lico

Scarselli

et al. 2022

2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)

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“…Phase-change memory (PCM) has arisen as a promising technology for the future of non-volatile memories (NVMs), due to its compatibility with CMOS fabrication processes, its high throughput and read/write endurance [1]. Specifically, the embedded PCM (ePCM) technology reduces process complexity, including at the same time high-power and high-voltage integrated elements [2], [3].…”

Section: Introductionmentioning

confidence: 99%

Phase-Change Memory in Neural Network Layers with Measurements-based Device Models

Paolino

Antolini

Pareschi

et al. 2022

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

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The search for energy efficient circuital implementations of neural networks has led to the exploration of phasechange memory (PCM) devices as their synaptic element, with the advantage of compact size and compatibility with CMOS fabrication technologies. In this work, we describe a methodology that, starting from measurements performed on a set of real PCM devices, enables the training of a neural network. The core of the procedure is the creation of a computational model, sufficiently general to include the effect of unwanted nonidealities, such as the voltage dependence of the conductances and the presence of surrounding circuitry. Results show that, depending on the task at hand, a different level of accuracy is required in the PCM model applied at train-time to match the performance of a traditional, reference network. Moreover, the trained networks are robust to the perturbation of the weight values, up to 10% standard deviation, with performance losses within 3.5% for the accuracy in the classification task being considered and an increase of the regression RMS error by 0.014 in a second task. The considered perturbation is compatible with the performance of state-of-theart PCM programming techniques.

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A 32-KB ePCM for Real-Time Data Processing in Automotive and Smart Power Applications

Cited by 18 publications

References 17 publications

Characterization and Programming Algorithm of Phase Change Memory Cells for Analog In-Memory Computing

Characterization and Programming Algorithm of Phase Change Memory Cells for Analog In-Memory Computing

Phase-change memory cells characterization in an analog in-memory computing perspective

Phase-Change Memory in Neural Network Layers with Measurements-based Device Models

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