A 32-bit RISC-V AXI4-lite bus-based microcontroller with 10-bit SAR ADC

Duran, Ckristian; Rueda, D. Luis; Castillo, Giovanny; Agudelo, Anderson; Rojas, Camilo; Chaparro, Luis Carlos Guayacán; Hurtado, Harry; Romero, Juan; Ramirez, Wilmer; Gomez, Hector; Ardila, Javier; Rueda, Luis Eduardo; Hernández, Humberto Escalante; Sánchez-Amaya, J.M.; Roa, Elkim

doi:10.1109/lascas.2016.7451073

Cited by 15 publications

(2 citation statements)

References 4 publications

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“…For small low-power energy-efficient 32-bit RISC-V microprocessors, although there were plenty of IP cores presented in FPGAs as reviewed by R. Höller et al in June 2019 [19], silicon proof publications were still limited. The worthmention 32-bit RISC-V chip measurement publications can be listed are the Parallel Ultra-Low Power (PULP) SoC in 2016 [20], PULPv2 SoC in 2017 [21], the low-power microcontroller intended for Internet of Things (IoT) in 2016 [22] and 2017 [23], the FE310-G000 in 2017 [24], and the FE310-G002 in 2019 [25]. In this paper, a 32-bit RISC-V microcontroller is presented and measured.…”

Section: Risc-v Is An Open-source Isa That Was First Presented By Thementioning

confidence: 99%

Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB)

Hoang

Duran

Nguyen

et al. 2020

IEICE Electron. Express

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In this paper, a 32-bit RISC-V microcontroller in a 65-nm Silicon-On-Thin-BOX (SOTB) chip is presented. The system is developed based on the VexRiscv Central Processing Unit (CPU) with the Instruction Set Architecture (ISA) extensions of RV32IM. Besides the core processor, the System-on-Chip (SoC) contains 8KB of boot ROM, 64KB of on-chip memory, UART controller, SPI controller, timer, and GPIOs for LEDs and switches. The 8KB of boot ROM has 7KB of hard-code in combinational logics and 1KB of a stack in SRAM. The proposed SoC performs the Dhrystone and Coremark benchmarks with the results of 1.27 DMIPS/MHz and 2.4 Coremark/MHz, respectively. The layout occupies 1.32-mm 2 of die area, which equivalents to 349,061 of NAND2 gate-counts. The 65-nm SOTB process is chosen not only because of its low-power feature but also because of the back-gate biasing technique that allows us to control the microcontroller to favor the low-power or the high-performance operations. The measurement results show that the highest operating frequency of 156-MHz is achieved at 1.2-V supply voltage (V DD) with +1.6-V back-gate bias voltage (V BB). The best power density of 33.4-W/MHz is reached at 0.5-V V DD with +0.8-V V BB. The least current leakage of 3-nA is retrieved at 0.5-V V DD with −2.0-V V BB .

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Section: Risc-v Is An Open-source Isa That Was First Presented By Thementioning

confidence: 99%

Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB)

Hoang

Duran

Nguyen

et al. 2020

IEICE Electron. Express

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“…No Data "ND" fields in these tables correspond to parameters that could not be inferred from the published data. The architecture reported in [3], [4] was developed in a 130nm technology, implements a RV32IM ISA, an AXI-LITE, and an APB bus. In [5], three cores: Riscy(RV32IM+DSP), Zero-Riscy(RV32IM) and Micro-Riscy(RV32E), implemented in 65nm and embedded in a PULPino platform are reported.…”

Section: Evaluation Of Siwa's Performancementioning

confidence: 99%

Siwa: a RISC-V RV32I based Micro-Controller for Implantable Medical Applications

García-Ramírez

Chacón-Rodríguez

Castro-González

et al. 2020

2020 IEEE 11th Latin American Symposium on Circuits &Amp; Systems (LASCAS)

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The design of Siwa 1 , a compact low power custom system on chip (SoC), targeted for implantable/wearable applications, is reported in this paper. Siwa is based on a RISC-V RV32I architecture. It has a centrally controlled non-pipelined structure, and it includes a control interface for an integrated sensing and stimulation device for biological tissues as well as standard communication interfaces. Siwa was developed from scratch using System Verilog, and implemented in a 180nm CMOS technology; Siwa includes a latch based register file c apable to read and write in one clock cycle with an area 30% smaller and a power consumption 25% lower with respect to an equivalent flip flop implementation; also, it has an estimated average power consumption of 70μW (48pJ/cycle) which is comparable to other micro-controllers commonly used in IMD applications.

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