A 31-$\mu$ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS

Abstract

This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. A fringecapacitor-based digital-to-analog converter (C-DAC) array is used to regulate the starting supply voltage of the constant discharging slope fed to a fixed-threshold comparator. The DTC operation mechanism is analyzed and design tradeoffs are investigated. The proposed DTC consumes merely 31 µW from a 1-V supply when clocked at 40 MHz, while achieving a fine resolution of 148 fs over a 9-bit range. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.96/1.07 LSB.

Interchannel Mismatch Calibration Techniques for Time-Interleaved SAR ADCs

“…By merging (22) and ( 23), we can find the total SNR as Using (25) and for a 12-bit 16-channel TI ADC with an input frequency of f in = 3.2 GHz (outlined as the "case-study" hereafter 2 ), a constraint of an SNR degradation lower than 1.5 dB imposes σ ∆T < 11.5 fs.…”

“…1) Analog: Analog correction of the timing error is usually performed using a variable-delay line (VDL). A VDL is basically a digital-to-time converter (DTC) that delays the input clock by a certain amount that is controlled by a digital code [25] [26]. To adjust the skewed clocks of the sub-ADCs of a TI ADC, each clock signal is delayed by a VDL placed just before the sampling switch of the corresponding sub-ADC.…”

“…In [1], a degenerated inverter is used where the degeneration resistor can be adjusted by a variable resistor. A constant slope method reported in [25] can provide a fine resolution of 100 fs with a 9-bit range.…”

“…The input signal used for calibration is a triangle signal with a frequency of f calib = f s /16. The resolution of the calibration, which is basically the resolution of the DTC, is set to 10 fs (this can be achieved by the DTC proposed in [6] or [31]). Random mismatch is also added to the DTC, in such a way that the maximum peak-to-peak INL is about 1LSB (i.e.…”

A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS

“…As a result, the worst-case fractional spur was reduced to −56 dBc with an rms jitter of 1.98 ps, while burning 670 μW. To further improve the INL of the DTC, a DAC-based constant-slope DTC architecture can be considered [6], [17], [21], [22]. In [6], the ADPLL using an isolated DAC-based constant-slope DTC with sub-1 ps INL achieves a worst-case fractional spur of −56 dBc and rms jitter of 0.53 ps, while consuming 980 μW, resulting in an excellent FoM of −246 dB.…”