A 300-MOPS Video Signal Processor With A Parallel Architecture

Minami, Toshihiro; Yamauchi, Hironori; Tashiro, Yutaka; Kasai, R.; Takahashi, Jun; Hamaguchi, S.; Endo, K.; Tajiri, T.

doi:10.1109/isscc.1991.689148

Cited by 26 publications

(5 citation statements)

References 6 publications

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“…The same arguments are valid in the case of SIMD-type architectures (see Cypher and Sanz [57] or e.g., survey in [61] Hence, the image analysis community started to consider, as a possible execution platform for mean and high granularity algorithms, in the late 1980s, programmable, multiprocessor, one-chip architectures. See for example [62], [63] or the survey of multiprocessor architectures with shared and distributed memory [64]. For another example and additional references, see a motion estimation on a set of video signal processors by De Greef et al [65], or watershed segmentation in Moga et al [66], Noguet [67], or Bieniek [68].…”

Section: Architecturementioning

confidence: 99%

Embedded Real-Time Architecture for Level-Set-Based Active Contours

Dejnozkova

Dokládal

2005

EURASIP J. Adv. Signal Process.

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Methods described by partial differential equations have gained a considerable interest because of undoubtful advantages such as an easy mathematical description of the underlying physics phenomena, subpixel precision, isotropy, or direct extension to higher dimensions. Though their implementation within the level set framework offers other interesting advantages, their vast industrial deployment on embedded systems is slowed down by their considerable computational effort. This paper exploits the high parallelization potential of the operators from the level set framework and proposes a scalable, asynchronous, multiprocessor platform suitable for system-on-chip solutions. We concentrate on obtaining real-time execution capabilities. The performance is evaluated on a continuous watershed and an object-tracking application based on a simple gradient-based attraction force driving the active countour. The proposed architecture can be realized on commercially available FPGAs. It is built around general-purpose processor cores, and can run code developed with usual tools

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Section: Architecturementioning

confidence: 99%

Embedded Real-Time Architecture for Level-Set-Based Active Contours

Dejnozkova

Dokládal

2005

EURASIP J. Adv. Signal Process.

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“…The integration of more multi-function systems into one chip monolithic IC is currently under the successive progress. Up to now, real time image processors with functions such as coding, vector quantization, motion compensation, filtering, edge detection, and so on, have been developed [1], [2]. However, the chip size of these processors is large and these have the disadvantage of operating at greatly large power dissipation of over 1 W. These also need A/D and D/A conversion circuits, which bring larger power dissipation when they are integrated with main processors.…”

Section: Introductionmentioning

confidence: 99%

A High-Speed CMOS OP Amplifier with a Dynamic Switching Bias Circuit

Wakaumi

2013

SICE Journal of Control, Measurement, and System Integration

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: This paper presents a high-speed CMOS operational amplifier (OP Amp) with a dynamic switching bias circuit, capable of processing video signals of over 2 MHz with decreased dissipated power. The OP Amp was designed to operate at a 10 MHz dynamic switching rate, and was shown in simulations to have a dissipated power of 66 % of conventional continuous operation. This OP Amp was applied to a switched capacitor (SC) non-inverting amplifier with a gain of 2, and its high-speed 10 MHz dynamic switching operation, capable of processing video signals, was demonstrated. By increasing the switching duty ratio to 70 %, its power dissipation decreased to 56 % of normal operation. Some inaccuracy in the SC amplifier performance resulted mainly from the limited open loop gain of the OP Amp. This circuit configuration should be extremely useful in realizing low-power wide-band signal processing ICs.

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“…Using this RTL model for functional simulations, the number of required clock cycles for processing of one picture element in the video data stream has been derived for a PE. This processing time for each task of a hybrid coding scheme as well as the communication As shown in [ll], based on Table 1,and for a system clock rate fcLK a MIMD multiprocessor system, whichconsists of N PES, can process all source rates Rs in real-time, with Under the assumption of recent submicron technologies a system clock rate of 40 MHz can be achieved [9,10]. Considering a decoder (IQ, IDCr, REC, WO) requires half computation power when compared to the coder, two PES are needed for the signal processing part of a hybrid coder and decoder at a frame rate of 10 Hz (source rate Rs = 1.52 Mpel/s).…”

Section: Architecture Of a Programmable Processing Elementmentioning

confidence: 99%

“…Several of thesesystemsconsist of multipleprogrammableprocessing elements (PES). The PES can be organized in apipeline [5], or operate in parallel [6,7,8,9,10,11]. The parallel architectures are based on SIMD (Single Instruction Multiple Data) [6] as well as MIMD (Multiple Instruction Multiple Data) [7,8,9,10, …”

Section: Introductionmentioning

confidence: 99%

A VLSI based multiprocessor architecture for video signal processing

Jeschke¹,

Gaedke²,

Pirsch³

[Proceedings] 1992 IEEE International Symposium on Circuits and Systems

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This paper discusses a VLSI based multiprocessor architecture for real-time processing of video coding applications. The architecture consists of multiple identical processing elements and is characterized as MIMD (Multiple Instruction Multiple Data). The architecture of a processing element is based on astandardprocessor core, e.g. a RISCprocessor, and a low level coprocessor. The low level coprocessor is adapted to parallel processing of convolution-like operations. The performance of the architecture is discussedwithrespectto the processing time for hybrid coding algorithms as well as to the required silicon area.

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A 300-MOPS Video Signal Processor With A Parallel Architecture

Cited by 26 publications

References 6 publications

Embedded Real-Time Architecture for Level-Set-Based Active Contours

Embedded Real-Time Architecture for Level-Set-Based Active Contours

A High-Speed CMOS OP Amplifier with a Dynamic Switching Bias Circuit

A VLSI based multiprocessor architecture for video signal processing

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