A 300-MHz CMOS voltage-controlled ring oscillator

Enam, S.K.; Abidi, A.A.

doi:10.1109/4.50320

Cited by 45 publications

(6 citation statements)

References 3 publications

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“…Hence the optimum gear-shifting minimizing at the time instance can be written as (13) Now, consider . Substituting (6) into (11) and the orthogonalities in (9) yield (14) In practice, it is difficult to evaluate the optimum gain sequence in (13), since in most real applications we do not know the input jitter variance and the reference input phase . To obtain practically useful expression of , we consider the following ZPS operation.…”

Section: Table I Algorithm For Computing An Optimum Gear-shifting Seqmentioning

confidence: 99%

“…Then, we have Since minimizing can be obtained by is independent of , and is . and are Now, as summarized in Table I, the calculation of at 3, 4, can be performed using (4), (10), (13), and (14), under the initial conditions. From (10) and 14, it is not difficult to see that under the ZPS assumption, both and are multiples of for all .…”

Section: Table I Algorithm For Computing An Optimum Gear-shifting Seqmentioning

confidence: 99%

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Optimum phase-acquisition technique for charge-pump PLL

Roh

Lee

Kim

1997

IEEE Trans. Circuits Syst. II

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In this paper, we propose a new optimum phaseacquisition algorithm controlling the loop gain of a chargepump PLL (CP-PLL) in the sense of the MMSE criterion. A set of recursive difference equations minimizing rms jitter of output phase is derived to obtain an optimum gear-shifting sequence with a zero-phase start (ZPS) assumption. It is shown that the optimum gear-shifting sequence is independent of the variance of the input phase jitter. A procedure for applying this sequence to the design of CP-PLL circuits is described. Both behavioral simulation and HSPICE circuit-level simulation demonstrate that the proposed design leads to an efficient CP-PLL having both fast acquisition and significant jitter reduction characteristics. The optimal gear-shifting CP-PLL outperforms the conventional CP-PLL's. These methods can be used for clock recovery applications such as data communication receivers, disk drive read/write channels, and local area networks, as well as for other applications requiring very short initial preamble periods.

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Section: Table I Algorithm For Computing An Optimum Gear-shifting Seqmentioning

confidence: 99%

Section: Table I Algorithm For Computing An Optimum Gear-shifting Seqmentioning

confidence: 99%

Optimum phase-acquisition technique for charge-pump PLL

Roh

Lee

Kim

1997

IEEE Trans. Circuits Syst. II

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“…Different types of delay cells have been reported in the literature for oscillator design including multiple-feedback loops, dual-delay paths, and single ended delays [11][12][13][14][15][16][17][18][19][20]. Delay cells have been implemented by different approaches like inverter stages, latches, cross-coupled cells and so forth.…”

Section: Isrn Electronicsmentioning

confidence: 99%

A Low Power Voltage Controlled Oscillator Design

Kumar

2013

ISRN Electronics

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The performance of voltage controlled oscillator (VCO) is of great importance for any telecommunication or data transmission network. Here, voltage controlled oscillators (VCOs) using three-transistor NAND gates have been designed. New delay cell with three-transistor NAND gate has been used for designing the ring based VCO circuits. Three-, five-, and seven-stage VCOs have been proposed. Output frequency has been controlled with supply voltage variation from 1.8 V to 2.4 V. Three stage VCO shows output frequency variation in the range of 3.2909 GHz to 4.2280 GHz whereas power consumption varies in the range of 335.4071 W to 486.1816 W. Five-stage VCO depicts frequency in the range of 1.9406 GHz to 2.5769 GHz with power consumption variation from 559.0118 W to 810.3027 W. Moreover a seven-stage VCO shows frequency variation from 1.3984 GHz to 1.8077 GHz. Power consumption of seven-stage VCO varies from 782.6165 W to 1134.400 W. Phase noise results for these VCOs have also been obtained. Power consumption, output frequency, and phase noise results of proposed circuits have been compared with earlier reported circuits, and the proposed circuits show significant improvements.

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“…Earlier designs have also incorporated phase interpolation for speed-up in ring buffer oscillators. One of these is a VCO described in [26], where the phase interpolation ratio is variable, and is used to control frequency while allowing speed-up. However, that design was very asymmetric and 49 unsuitable for uniform phase applications such as ours.…”

Section: Vcosmentioning

confidence: 99%

SiGe HBT BiCMOS for 2-160 Gb/s Next Generation Internet (NGI)

McDonald¹

2003

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A 300-MHz CMOS voltage-controlled ring oscillator

Cited by 45 publications

References 3 publications

Optimum phase-acquisition technique for charge-pump PLL

Optimum phase-acquisition technique for charge-pump PLL

A Low Power Voltage Controlled Oscillator Design

SiGe HBT BiCMOS for 2-160 Gb/s Next Generation Internet (NGI)

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