A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

Nedovic, Nikola; Kristensson, Anders; Parikh, Samir; Reddy, Subodh; McLeod, Scott; Tzartzanis, N.; Kanda, Kensuke; Yamamoto, Takuji; Matsubara, S.; Kibune, Masaya; Doi, Yoshihiro; Ide, Satoshi; Tsunoda, Yukito; Yamabana, T.; Shibasaki, Takayuki; Tomita, Yoshihiro; Hamada, Tomoko; Sugawara, Mariko; Ikeuchi, Tadashi; Kuwata, N.; Tamura, Hirotaka; Ogawa, J.; Walker, William W.

doi:10.1109/jssc.2010.2057970

Cited by 20 publications

(1 citation statement)

References 15 publications

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“…However, The signal frequency-dependent insertion loss in serial link channels has become the major limiter as skin effect, dielectric loss and coupling loss existing in the communication channels, causing intersymbol interference (ISI) which is the bottleneck for high speed-rate and long distance communication. In order to maximize the channel bandwidth utilization rate and improve the performance of transmission system, equalization technologies such as decision feedback equalizer (DFE) [3,4,7,9] and continuous-time equalizer (CTLE) [2,5,6,8,10] have been utilized to compensate the non-ideal characteristic in the receiver side. The equalizer can compensate the useful frequency component in the Nyquist frequency range, and restrain ISI even with channel conditions and process-voltage-temperature variations.…”

Section: Introductionmentioning

confidence: 99%

A high efficient CTLE for 12.5 Gbps receiver of JESD204B standard

Chen

Gong

et al. 2018

IEICE Electron. Express

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A 12.5 Gbps continuous-time linear equalizer circuit (CTLE) constructed with two stage equalizer, three stages of limiting amplifier and designed in 55 nm CMOS technology for high speed serial interface of JESD204B standard is presented. Beside using degeneration RC pair to compensate low pass response of the channel and high frequency signal loss, the first equalizer also utilizes inductive shunt peaking technology to further extend the bandwidth of input signals. The proposed circuit was simulated with post layout parasitic extraction and achieves around 20 ps peak-to-peak jitter, 1.08 V voltage swing and a data rate of 12.5 Gbps through 10-inch FR-4 PCB trace with the characteristic of low equalization power consumption.

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