A 3 GS/s &gt;55 dBFS SNDR Time-Interleaved RF Track and Hold Amplifier with &gt;67 dBc SFDR up to 3 GHz in 22FDX

Wittenhagen, Enne; Artz, Patrick James; Scholz, Philipp; Gerfers, Friedel

doi:10.1109/rfic51843.2021.9490479

Cited by 10 publications

(4 citation statements)

References 5 publications

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“…The voltage difference between vin and vout is experienced by CX, causing the signal-dependent charge QX to be stored in its nonlinear capacitance during the track phase. Similar to Cgs, the capacitance of CX can also be expressed in terms of vgs, as shown in (15). As a result, QX can be expressed in relation to vin, as shown in (16).…”

Section: ) Cross-coupled Capacitormentioning

confidence: 99%

An Active Track and Hold Circuit With Linearity Enhancement Technique and Its Analysis Using Volterra Series

Jang,

Lee,

Kim

2024

IEEE Access

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This paper presents a comprehensive analysis of active track and hold (T/H) circuits that utilize switched source followers and time-divided post-distortion cancellation. In the track phase, the circuit acts as an active buffer and transfers an input signal, including track-mode distortion caused by the buffer's nonlinear transconductance. In the hold phase, the transferred signal is held but hold-mode distortion is added, including hold-mode feed-through and hold pedestal error, causing deterioration of the circuit's linearity. The timedivided post-distortion cancellation technique improves the circuit's linearity by cancelling the track-mode distortion with the hold-mode distortion. Volterra series analysis offers a comprehensive understanding of the operation. 17 sample chips were measured to verify stable cancellation operation. It shows a mean SFDR value of 77.1 dB and a standard deviation of 1.8 dB with 9mW power consumption.

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Section: ) Cross-coupled Capacitormentioning

confidence: 99%

An Active Track and Hold Circuit With Linearity Enhancement Technique and Its Analysis Using Volterra Series

Jang,

Lee,

Kim

2024

IEEE Access

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“…Figure 2b shows the V TH controllability, by applying voltages up to 3 V to the body of the nMOS (-3 V for the pMOS) altering the threshold voltage by 83 mV/V. This benefit is used for dynamic as well as static body-biasing as reported in [6]- [8].…”

Section: Nm Cmos Soi Technologymentioning

confidence: 99%

“…The FE-buffer is depicted in Fig. 3a, where a pseudodifferential push-pull architecture with bootstrapped drain nodes is used [1], [6], [10]. With this architecture, the FEbuffer output resistance is minimized.…”

Section: Circuit Designmentioning

confidence: 99%

“…This article is an expanded version of the RFIC paper [6] including an introduction to the used 22 nm CMOS SOI technology and a more in-depth circuit analysis of the 3 GS/s low power high-linear open-loop pseudo-differential FE buffer together with the highly-linear TI track-and-hold (TaH). The proposed TaH amplifier employs both static as well as dynamic body-biasing to control the common-mode, reduce the power, and to increase the linearity of the FE-sampler.…”

Section: Introductionmentioning

confidence: 99%

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A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI

Wittenhagen

Artz

Scholz

et al. 2022

IEEE Open J. Solid-State Circuits Soc.

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In this article, a 3 GS/s Time-Interleaved (TI) RF Track-and-Hold (TaH) amplifier designed in a 22 nm SOI technology is presented. The TaH amplifier is designed to drive an ADC, which can be either two pipeline-ADCs or two rows of SAR-ADCs. Both TI TaH are driven by a single RF-matched wide-band bulk-controlled Front-End (FE) buffer. The measured TaH amplifier has a SFDR beyond 70 dBc up to 2.5 GHz and remains above 67 dBc till 3 GHz enabling sub-sampling. An overall system bandwidth of 4.5 GHz is achieved with a SNR above 55 dBFS. The ultra-low-jitter clock regeneration has only 45 fs rms jitter not limiting the SNR up to 3 GHz. Two-tone and multi-tone measurements reveal a third intermodulation and inter-band non-linearity with >72 dBFS and >82 dBFS respectively. Off-chip calibration of offset/gain mismatch and time-skew between both TaH-lanes reduce interleaving spurs >75 dBFS utilizing a 37-tap fractional delay FIR filter. The efficient body-bias control of the technology is used to dynamically body-bias the TaH sample-switch increasing bandwidth by 10% improving settling performance while at the same time the leakage decreases. Static body-biasing is also applied to the common-mode-feedback by using the bulk as an control node. The TaH amplifier including the clock generation consumes only 178 mW from a triple 2 V/0.9 V/-0.8 V supply.

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A TI 12 GS/s Sampled Beam-Forming Receiver for a $2\times 2$ Antenna-Array with 69 dBc SFDR

Wittenhagen

Kurth

Kaiser

et al. 2022

2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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A 3 GS/s >55 dBFS SNDR Time-Interleaved RF Track and Hold Amplifier with >67 dBc SFDR up to 3 GHz in 22FDX

Cited by 10 publications

References 5 publications

An Active Track and Hold Circuit With Linearity Enhancement Technique and Its Analysis Using Volterra Series

An Active Track and Hold Circuit With Linearity Enhancement Technique and Its Analysis Using Volterra Series

A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI

A TI 12 GS/s Sampled Beam-Forming Receiver for a $2\times 2$ Antenna-Array with 69 dBc SFDR

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