A 3-D TCAD Framework for NBTI—Part I: Implementation Details and FinFET Channel Material Impact

Tiwari, Ravi; Parihar, Narendra; Thakor, Karansingh; Wong, Hiu Yung; Motzny, Steve; Choi, Munkang; Moroz, Victor; Mahapatra, S.

doi:10.1109/ted.2019.2906339

Cited by 49 publications

(5 citation statements)

References 33 publications

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“…The NBTI stress-induced threshold voltage shifts and transconductance peak decreases are -80.6 mV and 8.4% respectively for unirradiated I/O pMOSFET. The observed threshold voltage shift is contributed to positively charged oxide trapped charge and interface traps after irradiation and NBTI stress in pMOSFET [19]. The transconductance degradation is mainly result from the interface traps or interface-like traps, which is related to the increase of the effective Coulombic scattering [20].…”

Section: A Nbti Effects Coupled By Tid Irradiation In Pdsoi Pmosfetmentioning

confidence: 99%

Research on Negative Bias Temperature Instability Effects Under the Coupling of Total Ionizing Dose Irradiation for PDSOI MOSFETs

et al. 2021

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The degradation mechanisms for pMOSFETs from a 130 nm partially-depleted silicon on insulator (PDSOI) technology under the combined effects of total ionizing dose (TID) and negative bias temperature instability (NBTI) are investigated. The TID and NBTI related degradations show an opposite trend as gate oxide scaling, which implies the different traps are activated during irradiation and NBTI stress. The radiation-induced traps can affect the NBTI effect of pMOSFET, especially for the ON bias irradiation. The irradiated I/O pMOSFET shows a smaller threshold voltage shift than the un-irradiated device under the same NBTI stress at the early stress stage. It may be contributed to the enhanced Fowler-Nordheim electron injection during NBTI stressing after ON bias irradiation. But the irradiation also increases the time exponent n from 0.11 to 0.13 for Core pMOSFETs and from 0.18 to 0.20 for I/O devices. It means that the NBTI degradations become worse after ON bias irradiation in a long time scale. This phenomenon is attributed to the change of trap characteristics caused by irradiation. As a result, the NBTI lifetime of Core device is reduced by nearly three orders of magnitude and the lifetime of I/O device is reduced by five times after ON bias irradiation at the rated operating voltage.INDEX TERMS MOSFET, negative bias temperature instability, silicon on insulator, total ionizing dose effect.

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Section: A Nbti Effects Coupled By Tid Irradiation In Pdsoi Pmosfetmentioning

confidence: 99%

Research on Negative Bias Temperature Instability Effects Under the Coupling of Total Ionizing Dose Irradiation for PDSOI MOSFETs

et al. 2021

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“…For the ferroelectric material to fully polarize, a sufficient electric field across the ferroelectric layer is necessary [20]. The electric field enhancement in the conventional FinFET structure of Si substrate and HfO2 gate insulator was understood using technology computer-aided design (TCAD) simulation (Synopsys Sentaurus) [21]. The simulation condition was VG=5 V, VD = 0 V, VS = 0 V, and HfO2 layer thickness=2 nm.…”

Section: Planarmentioning

confidence: 99%

The Research of Occupation of Jeonju-Castle by Donghak Peasant' Army and Samrye Haeng-yeongso(Camp)

Park¹,

전문위원²

2020

JEONBUK SAHAK ; The Jeonbuk Historical Journal

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We have experimentally demonstrated the effectiveness of beta-gallium oxide (β-Ga2O3) ferroelectric fin field-effect transistors (Fe-FinFETs) for the first time. Atomic layer deposited (ALD) hafnium zirconium oxide (HZO) is used as the ferroelectric layer. The HZO/β-Ga2O3 Fe-FinFETs have wider counterclockwise hysteresis loops in the transfer characteristics than that of conventional planar FET, achieving record-high memory window (MW) of 13.9 V in a single HZO layer. When normalized to the actual channel width, FinFETs show an improved ION/IOFF ratio of 2.3×10 7 and a subthreshold swing value of 110 mV/dec. The enhanced characteristics are attributed to the low-interface state density (Dit), showing good interface properties between the β-Ga2O3 and HZO layer. The enhanced polarization due to larger electric fields across the entire ferroelectric layer in FinFETs is validated using Sentaurus TCAD. After 5×10 6 program/erase (PGM/ERS) cycles, the MW was maintained at 9.2 V, and the retention time was measured up to 3×10 4 s with low degradation. Therefore, the ultrawide bandgap (UWBG) Fe-FinFET was shown to be one of the promising candidates for highdensity non-volatile memory devices.

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“…To this end, simulations are needed to predict functionalities and finally increase the feedback cycle from device measurement to fabrication. Simulation tools are extensively used throughout the advanced semiconductor industry for high complexity devices, as for example technology computer-aided design which is used for transistor, photo detector and miniature solar cell designs [19][20][21].…”

Section: Introductionmentioning

confidence: 99%

Tailoring potentials by simulation-aided design of gate layouts for spin qubit applications

Inga¹,

Neul²,

Kammerloher³

et al. 2023

Preprint

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A 3-D TCAD Framework for NBTI—Part I: Implementation Details and FinFET Channel Material Impact

Cited by 49 publications

References 33 publications

Research on Negative Bias Temperature Instability Effects Under the Coupling of Total Ionizing Dose Irradiation for PDSOI MOSFETs

Research on Negative Bias Temperature Instability Effects Under the Coupling of Total Ionizing Dose Irradiation for PDSOI MOSFETs

The Research of Occupation of Jeonju-Castle by Donghak Peasant' Army and Samrye Haeng-yeongso(Camp)

Tailoring potentials by simulation-aided design of gate layouts for spin qubit applications

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