A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps

Lu, Ping; Liscidini, Antonio; Andreani, Pietro

doi:10.1109/jssc.2012.2191676

Cited by 94 publications

(32 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…To configure the RO in the gateable mode, important design adjustments of the ring oscillator are needed. We can either introduce enable transistors into the delay element [21], [26], [28], [29], or we can use gating logic [27].…”

Section: A Gateable Ring Oscillatormentioning

confidence: 99%

“…if comes prior to if comes prior to (4) Either a DFF [24], or an arbiter [20], [21], [26], [28] can be used to perform this function. The most important parameter of a time comparator is the offset time, analogous to the voltage offset in the voltage comparator.…”

Section: B Arbitermentioning

confidence: 99%

“…Consequently, the in-band phase noise has been filtered out and the effective resolution of the TDC can be improved. The noise shaping method has been used in both the Vernier GRO TDC [26], [27] and the 2-D Vernier GRO TDC [28]. However, the resolution of the regular GRO TDC still is bounded to the propagation delay of an inverter unless a Vernier scheme like that in [26]- [28] is used.…”

mentioning

confidence: 99%

See 2 more Smart Citations

A Low-Power Gateable Vernier Ring Oscillator Time-to-Digital Converter for Biomedical Imaging Applications

Zhou

Deen

Peng

2016

IEEE Trans. Biomed. Circuits Syst.

View full text Add to dashboard Cite

In this paper, a high resolution, high precision and ultra-low power consumption time-to-digital converter (TDC) is presented. The proposed TDC is based on the gateable Vernier ring oscillator architecture. Fine resolution is achieved through two ring oscillators arranged in the Vernier configuration. This TDC employs a single-transition end-of-conversion detection circuit and turns off the ring oscillators whenever the conversion is completed to reduce power consumption. The prototype chip is fabricated in a standard 130 nm digital CMOS process and its area is only 0.03 mm(2). Using a 1.2 V supply, the TDC achieves a resolution of 7.3 ps, a single-shot precision of 1.0LSB, and an average power consumption of 1.2 mW. A root-mean-square integral nonlinearity (INL) of 1.2 LSB is obtained with the help of an INL look-up-table calibration. Compared to previously reported ring-oscillator based TDCs, the proposed design achieves the lowest power consumption to date.

show abstract

Section: A Gateable Ring Oscillatormentioning

confidence: 99%

Section: B Arbitermentioning

confidence: 99%

mentioning

confidence: 99%

See 1 more Smart Citation

A Low-Power Gateable Vernier Ring Oscillator Time-to-Digital Converter for Biomedical Imaging Applications

Zhou

Deen

Peng

2016

IEEE Trans. Biomed. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…In a [10], a ring oscillator is frozen [12] by disabling the delay elements. While conventionally this is done by an external signal for all delay elements synchronously, the novel architecture uses the stop signal to freeze the start line in a linear Vernier delay line.…”

Section: Architecturementioning

confidence: 99%

“…An attempt to omit the power-hungry time capture circuitry is the Vernier Gated Ring Oscillator [10], where the delay stages are frozen by and external enable/disable signal. Wherever the signal was frozen in transition, the analog voltage value is preserved long enough to be read out by a counter.…”

Section: Introductionmentioning

confidence: 99%

A CMOS 0.23pj Freeze Vernier Time-To-Digital Converter

et al. 2013

View full text Add to dashboard Cite

Abstract-A novel Time-to-Digital Converter architecture for high resolution and low power is proposed. The Freeze Vernier Delay Line is a Vernier-type TDC, where the state of the slow delay line can be frozen by the fast delay line, omitting the powerhungry time capture elements like D-registers or arbiters that are usually employed in a Vernier TDC. The two main issues of the design, the charge kickback between the delay lines and the imperfect freezing are solved with extra circuitry. The overall TDC consists of inverters and transmission gates only. A proof-ofconcept design has been simulated in 90nm CMOS with a typical resolution of 10.05 ps, a dynamic energy consumption of 0.232 pJ per conversion and an area of 10.503 µm 2 .

show abstract

Low‐power, latch‐based multistage time‐to‐digital converter in 65 nm CMOS technology

Razmdideh

Saneei

2018

Circuit Theory & Apps

View full text Add to dashboard Cite

In this paper, a low-power and high-resolution latch-based time-to-digital converter (TDC) based on a multistage scheme is proposed. The proposed multistage TDC includes coarse, middle, and fine stages. The coarse stage is a new design of the flash TDC that is implemented by latches without using the delay cell. Also, the middle stage is a new design of the Vernier TDC with employed latches. The fine stage comprises parallel latches with different input loads.KEYWORDS high resolution, low power, TDC, VLSI | INTRODUCTIONHigh-precision time interval measurement is highly significant in many systems. Time-to-digital converter (TDC) is a system of time measurement, which converts the interval between 2 input pulses into a digital code. Time-to-digital converter has numerous applications, such as phase failure detection in the design of phase-locked loops. 1-5 The use of TDCs instead of phase comparator in phase-locked loop structure leads to removal of analog parts such as charge pump and loop filter. In addition, TDC is used in the structure of time-based analog to digital converters. 6,7 In this type of analog-to-digital converters, analog input voltage is turned into a time interval, and then the time interval is converted to a digital code through TDC. Also, TDC is used in medical imaging systems such as scanners, 8-11 other time of flight measurement methods, 12-14 and coupled with single photon avalanche diode array to build complementary metal oxide semiconductor image sensor. [15][16][17] A basic structure in design of TDC is flash TDC, which is composed of a delay line with several stages of buffers and comparators. 18 In this TDC, resolution is equal to delay of each buffer, which is the long delay. To enhance resolution, Vernier delay line structure was used. 19 The structure of this TDC is shown in Figure 1. This TDC is made up of several stages; each stage includes 2 different delay lines and a comparator. Resolution can be less than the delay of a buffer (resolution equivalent of difference in delay of 2 delay cells). In this structure, dynamic range is limited to the number of stages, and by adding extra stages, the dynamic range is increased. Because each stage is made up of 2 buffers and a comparator, power consumption of the circuit increases significantly. In addition, its linearity reduces as the number of stages increases. Two-dimensional Vernier TDC proposed in Vercesi et al 2 reduced the length of the delay lines to increase the efficiency compared with Vernier delay line TDC. However, this TDC had limited dynamic range and had serious problem in linearity. Three-dimensional Vernier space TDC 12 was introduced to increase dynamic range with minimizing the delay line. Vernier Ring TDC proposed in Yu et al 1 places the Vernier delay cells and arbiters in a ring format and reuses them for the measurement of the input time interval. This TDC achieves larger detectable range and fine time resolution, but has higher power consumption. Gated-Vernier TDC, which has 2 gated ring oscillators, acts as the...

show abstract

A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps

Cited by 94 publications

References 19 publications

A Low-Power Gateable Vernier Ring Oscillator Time-to-Digital Converter for Biomedical Imaging Applications

A Low-Power Gateable Vernier Ring Oscillator Time-to-Digital Converter for Biomedical Imaging Applications

A CMOS 0.23pj Freeze Vernier Time-To-Digital Converter

Low‐power, latch‐based multistage time‐to‐digital converter in 65 nm CMOS technology

Contact Info

Product

Resources

About