A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS

Toifl, Thomas; Ruegg, Michael; Inti, Rajesh; Menolfi, Christian; Brändli, Matthias; Kossel, Marcel; Buchmann, P.; Francese, Pier Andrea; Morf, Thomas

doi:10.1109/vlsic.2012.6243810

Cited by 17 publications

(11 citation statements)

References 2 publications

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“…The use of loop unrolling is often limited to tap‐1 as the number of slicers and summers increases exponentially with the number of taps. In recent DFE implementations, loop unrolling has also been used for first two taps to cope with 28 Gbps data rate [38] and first 3 taps to cope with 30 Gbps data rate [36, 37, 57]. As pointed out in [6, 60], the delay of the slicer could be long if its input is small.…”

Section: Design Challenges In Decision Feedback Equalisationmentioning

confidence: 99%

Design techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review

Yuan

Al-Taee

et al. 2014

IET Circuits, Devices & Systems

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This study provides a comprehensive review of decision feedback equalisation (DFE) for multi-giga-bit-per-second (Gbps) data links. The state-of-the-art of DFE for multi-Gbps serial links reported in the past decade are compiled and presented. The imperfection of wire channels, in particular, finite bandwidth, reflection and cross-talk and their impact on data transmission are investigated. The fundamentals of both near-end and far-end channel equalisation to combat the effect of the imperfection of wire channels at high frequencies are explored. A detailed examination of the principle, configuration, operation and limitation of DFE is followed. Design challenges encountered in design of DFE for multi-Gbps data links including timing constraints, sampling, error propagation, arithmetic operation, highly dispersive channels, power consumption and techniques and circuit implementations that address these challenges are studied. The need for adaptive DFE and the principles of adaptive DFE are investigated. Finally, the performance of various adaptive DFEs is examined and their pros and cons are compared.

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Section: Design Challenges In Decision Feedback Equalisationmentioning

confidence: 99%

Design techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review

Yuan

Al-Taee

et al. 2014

IET Circuits, Devices & Systems

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“…Loop-unrolling has been proven to be an effective technique in meeting the timing constraint of the tap-1 of DFE [19,[58][59][60]. High-order loop-unrolling also emerged when data rate exceeds 10 Gb/s, however, at the cost of high silicon consumption [10,11,61]. To relax the timing constraint and at the same time to lower the power consumption of the remaining DFE taps, the half rate approach is widely used [59].…”

Section: Channel Equalizationmentioning

confidence: 99%

“…To relax the timing constraint and at the same time to lower the power consumption of the remaining DFE taps, the half rate approach is widely used [59]. Quarter-rate approach was also deployed to further relax the timing constraint, however, at the cost of high silicon consumption [10,11,49,61]. Since DFE operation is based on the correct recovery of data, an error occurring in data slicing will propagate through the delay chain of the equalizer and affect subsequent data recovery decisions.…”

Section: Channel Equalizationmentioning

confidence: 99%

Design Techniques for High-Speed I/Os: Challenges and Opportunities

Yuan¹

2014

J Elec Electron Syst

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“…1(b). Various equalization techniques are widely used to compensate the signal distortion induced by the channel [3], [4], which can significantly improve the performance of the high-speed links. Equalization can significantly improve signal quality.…”

Section: Introductionmentioning

confidence: 99%

A Novel Decision Feedback Equalization Structure for Nonlinear High-Speed Links

Chu

Wang

et al. 2020

IEEE Access

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As the degree of nonlinearity in high-speed links becomes more and more serious, traditional decision feedback equalization (DFE) which is based on linear time-invariant assumption can no longer eliminate the inter-symbol interference effectively. In this paper, the shortcomings of traditional DFE structure for nonlinear high-speed links are first analyzed. Then, the multi-bit response (MBR) method is proposed to accurately construct the bit stream responses of the nonlinear high-speed links. Lastly, a novel DFE structure based on the MBR method is presented to improve the signal quality of the nonlinear high-speed links. The accuracy of the proposed method is verified by the simulation based on a nonlinear high-speed link model. Compared with traditional DFE, the proposed DFE structure can significantly improve the signal quality of the nonlinear high-speed links. As the degree of nonlinearity increases, the advantage of the proposed DFE becomes more prominent. INDEX TERMS Decision feedback equalization (DFE), inter-symbol interference (ISI), multi-bit response, nonlinearity, signal integrity.

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A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS

Cited by 17 publications

References 2 publications

Design techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review

Design techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review

Design Techniques for High-Speed I/Os: Challenges and Opportunities

A Novel Decision Feedback Equalization Structure for Nonlinear High-Speed Links

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