A 3.1 Gb/s 8<inline-formula> <tex-math notation="LaTeX">$\,\times\,$ </tex-math></inline-formula>8 Sorting Reduced K-Best Detector With Lattice Reduction and QR Decomposition

Abstract

This paper presents the VLSI implementation of a lattice-reduction-aided (LRA) detection system. The proposed system includes a QR decomposition, lattice reduction (LR) processor, and sorting-reduced (SR) K-best detector for 8 × 8 multiple-input multiple-output (MIMO) systems. The bit error rate of the proposed MIMO detection system only incurs approximately 3 dB of implementation loss compared with optimal maximum likelihood detection with 64-quadratic-amplitude modulation. The proposed processor can also support different throughput requirements by adjusting the stage number of LR. The SR K-best detector can achieve 3.1 Gb/s throughput with 0.24-ns latency. The throughput of the system reaches 585 Mb/s if one channel preprocessing can support 72 symbol detections. The corresponding energy per bit is 63 pJ/bit, which is the smallest value achieved to date. This paper presents the first VLSI implementation of a complete LRA K-best detector with an 8 × 8 dimension.Index Terms-K-best detector, lattice reduction (LR), multipleinput multiple-output (MIMO) detection.

Sub-optimal Deep Pipelined Implementation of MIMO Sphere Detector on FPGA

“…From the above analysis, the number of valid nodes varies across the search level, and this has been exploited for further enhancing the K-best algorithm in [17,19,20,23]. In those works, a larger K is used in early levels to avoid error propagation, and a smaller K in the top levels reduces computational complexity.…”

“…The simulated result shows a maximum throughput of 2.2 Gbps, which so far is the fastest hardware of FSD implementation in our record. K-best is another popular SD accelerator architecture and has been actively studied recently [13][14][15][16][17][18][19][20][21][22]. The K-Best SD is based on breadth-first search, which considers only the best (K) candidates at each level to be passed to the next level of the search tree.…”

“…Thus, ML could be considered a special case of K-best with a sufficiently large K [13]. The conventional K-best sphere detectors use the same K value at all levels [13][14][15][16][17][18], while recent developments offer more flexible and efficient designs [19][20][21][22]. Among those, several practical K-Best SD has been prototyped on hardware [16,17,[19][20][21][22]28] that show advantages over FSD in both complexity and throughput.…”

“…In [20], the variable K-best has been proposed to reduce the complexity without degrading the BER; the corresponding 180 nm VLSI implementation [20] exhibits a throughput of 1.5 Gbps. Furthermore, the sorting reduced K-best (SR K-best) detector was then proposed in [17], which is based on two methods of staging reduction and QR transform performed on complex numbers; the corresponding VLSI implementation on CMOS 90 nm achieves a throughput of up to 3.1 Gbps. In [21], Wu et al proposed a bounded selective spanning technique that effectively removes invalid nodes from the K best nodes, thus reducing the necessary computation compared to the prior works, though the implementation on FPGA achieves moderate throughput of 484.8 Mbps for a 4 × 4 MIMO detector.…”

Design and VLSI Implementation of a Reduced-Complexity Sorted QR Decomposition for High-Speed MIMO Systems

“…In recent years, there were many studies focusing on the implementation of SQRD. In reference [15][16][17][18][19][20][21], the SQRD is performed directly on the complex-valued matrix H for the complex-valued MIMO detection model. However, the subsequent MIMO detection in a complex-valued model is more complicated than the one in a real-valued model [22].…”