A 2Tb/s 6&amp;#x00D7;4 mesh network with DVFS and 2.3Tb/s/W router in 45nm CMOS

Salihundam, Praveen; Jain, Shailendra; Jacob, Tiju; Kumar, Smita; Erraguntla, Vasantha; Hoskote, Yatin; Vangal, Sriram; Ruhl, G.; Kundu, Partha; Borkar, Nitin

doi:10.1109/vlsic.2010.5560277

Cited by 14 publications

(13 citation statements)

References 4 publications

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“…The number of crosspoints is calculated according to the following formula. To calculate the area of a single crosspoint we use an empirical model where we first measure the crosspoint area of three router designs for which we have access to their crossbar area numbers [Kumar et al 2007a;Vangal et al 2008;Salihundam et al 2010]. We extract the crossbar area from the provided die photos.…”

Section: Area Analysismentioning

confidence: 99%

“…We extract the crossbar area from the provided die photos. The crossbar in Salihundam et al [2010] is implemented in 45nm technology. Its area is scaled to 65nm before calculating its crosspoint area.…”

Section: Area Analysismentioning

confidence: 99%

“…This means wire-dominated parts like a crossbar become lager relative to other components. As a real example, 5-port 144-bit routers occupy 1.17 mm 2 in 45nm technology [Salihundam et al 2010] which is not particularly small.…”

Section: Scalabilitymentioning

confidence: 99%

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Designing on-chip networks for throughput accelerators

Bakhoda

Kim

Aamodt

2013

ACM Trans. Archit. Code Optim.

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As the number of cores and threads in throughput accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network design. This article explores throughputeffective Network-on-Chips (NoC) for future compute accelerators that employ Bulk-Synchronous Parallel (BSP) programming models such as CUDA and OpenCL. A hardware optimization is "throughput effective" if it improves parallel application-level performance per unit chip area. We evaluate performance of future looking workloads using detailed closed-loop simulations modeling compute nodes, NoC, and the DRAM memory system. We start from a mesh design with bisection bandwidth balanced to off-chip demand. Accelerator workloads tend to demand high off-chip memory bandwidth which results in a many-to-few traffic pattern when coupled with expected technology constraints of slow growth in pins-per-chip. Leveraging these observations we reduce NoC area by proposing a "checkerboard" NoC which alternates between conventional full routers and half routers with limited connectivity. Next, we show that increasing network terminal bandwidth at the nodes connected to DRAM controllers alleviates a significant fraction of the remaining imbalance resulting from the many-to-few traffic pattern. Furthermore, we propose a "double checkerboard inverted" NoC organization which takes advantage of channel slicing to reduce area while maintaining the performance improvements of the aforementioned techniques. This organization also has a simpler routing mechanism and improves average application throughput per unit area by 24.3%.

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Section: Area Analysismentioning

confidence: 99%

Section: Area Analysismentioning

confidence: 99%

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Designing on-chip networks for throughput accelerators

Bakhoda

Kim

Aamodt

2013

ACM Trans. Archit. Code Optim.

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“…The 5-port router [5] uses 4 pipe stages, virtual cut-through switching for reduced mesh latency, and 144-bit bi-directional links to create the 2-D mesh on-die network. The first pipe stage includes link traversal and buffer-write for incoming packets.…”

Section: B Router Architecturementioning

confidence: 99%

“…Thus, frequency changes are much more common than voltage changes in power optimized software. Deterministic first-in-first-out (FIFO) based clock crossing units (CCFs) are used for synchronization across clocking domains [5]. Frequency aware read pointers ensure that the same FIFO location is not read from and written to simultaneously.…”

Section: Dvfsmentioning

confidence: 99%

A 48-core IA-32 processor with on-die message-passing and DVFS in 45nm CMOS

Howard

2010

2010 IEEE Asian Solid-State Circuits Conference

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This paper describes a microprocessor that integrates 48 IA-32 cores, 4 DDR3 memory channels, and a voltage regulator controller in a 6×4 2D-mesh network-on-chip topology. Located at each mesh node is a five-port packetswitched router shared between two cores. Core-to-core communication uses message passing while exploiting 384KB of on-die shared memory. Power management takes advantage of 8 voltage and 28 frequency islands to allow independent DVFS of cores and mesh. At the nominal 1.1V supply, cores operate at 1GHz and the 2D-mesh operates at 2GHz. As performance and voltage scales, the processor dissipates between 25W and 125W. The 567mm 2 processor is implemented in 45nm Hi-K CMOS and has 1.3 billion transistors.

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The fast evolving landscape of on-chip communication

Bertozzi

Dimitrakopoulos

Flich

et al. 2014

Des Autom Embed Syst

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As multi-core systems transition to the manycore realm, the pressure on the interconnection network is substantially elevated. The Network-on-Chip (NoC) is expected to undertake the expanding demands of the ever-increasing numbers of processing elements, whileat the same time-technological and application constraints increase the pressure for increased performance and efficiency with limited resources. Although NoC research has evolved significantly the last decade, essential questions remain un-answered and call for fresh research ideas and innovative solutions. In this paper, we summarize a selected set of NoC-related research challenges, with the hope to guide future development and trigger high-impact research progress.

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A 2Tb/s 6×4 mesh network with DVFS and 2.3Tb/s/W router in 45nm CMOS

Cited by 14 publications

References 4 publications

Designing on-chip networks for throughput accelerators

Designing on-chip networks for throughput accelerators

A 48-core IA-32 processor with on-die message-passing and DVFS in 45nm CMOS

The fast evolving landscape of on-chip communication

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