A 2nd-Order ΔΣAD Modulator Using Dynamic Analog Components with Simplified Operation Phase

Abstract

A 2nd-order ∆ΣAD modulator architecture is proposed to simplify the operation phase using ring amplifier and SAR quantizer. The proposed modulator architecture can guarantee the reset time for ring amplifier and relax the speed requirement on asynchronous SAR quantizer. The SPICE simulation results demonstrate the feasibility of the proposed 2nd-order ∆ΣAD modulator in 90 nm CMOS technology. Simulated SNDR of 95.70 dB is achieved while a sinusoid −1 dBFS input is sampled at 60 MS/s for the bandwidth is BW=470 kHz. The power consumption of the analog part in the modulator is 1.67 mW while the supply voltage is 1.2 V.

Experimental implementation of delta sigma AD modulator using dynamic analog components with simplified operation phase

“…In order to improve the operation speed of the above ÁAEAD modulator, we propose a modified ÁAEAD modulator architecture using ring-amplifier and SAR ADC for simplifying the operation phase [20]. As shown in Fig.…”

“…Its clock timing chart is shown in Fig. 3(c) [21]. Because the signal V U and V o2 are sampled during the same phase by SAR quantizer as shown in Fig.…”

“…In our previous work, we have proposed a ÁAEAD modulator using ring-amplifier and passive adder embedded SAR quantizer. SPICE simulation results show that the proposed modulator can be realized with simplified operation phase [20,21]. In this work, we report the detail of the circuit implementation and the experimental results of the proposed modulator.…”