“…An improved peak (32%) and backed-off (31%) PAE was observed with a maximum DE of 59%. This is also an improvement in the overall PAE from the classical DPA architecture (Figure 20) [9]. Under the constant bias condition, the Doherty PA peak PAE was 28% and showed a 3% degradation at back-off (25%), while the maximum drain efficiency measured was 48%.…”
Section: Transmitter Chainmentioning
confidence: 83%
“…An improved peak (32%) and backed-off (31%) PAE was observed with a maximum DE of 59%. This is also an improvement in the overall PAE from the classical DPA architecture ( Figure 20 ) [ 9 ].…”
This paper presents the design and implementation of a 28 GHz phased array transceiver for 5G applications using 22 nm FD-SOI CMOS technology. The transceiver consists of a four-channel phased array receiver and transmitter, which employs phase shifting based on coarse and fine controls. The transceiver employs a zero-IF architecture, which is suitable for small footprints and low power requirements. The receiver achieves a 3.5 dB NF with a 1 dB compression point of −21 dBm and a gain of 13 dB.
“…An improved peak (32%) and backed-off (31%) PAE was observed with a maximum DE of 59%. This is also an improvement in the overall PAE from the classical DPA architecture (Figure 20) [9]. Under the constant bias condition, the Doherty PA peak PAE was 28% and showed a 3% degradation at back-off (25%), while the maximum drain efficiency measured was 48%.…”
Section: Transmitter Chainmentioning
confidence: 83%
“…An improved peak (32%) and backed-off (31%) PAE was observed with a maximum DE of 59%. This is also an improvement in the overall PAE from the classical DPA architecture ( Figure 20 ) [ 9 ].…”
This paper presents the design and implementation of a 28 GHz phased array transceiver for 5G applications using 22 nm FD-SOI CMOS technology. The transceiver consists of a four-channel phased array receiver and transmitter, which employs phase shifting based on coarse and fine controls. The transceiver employs a zero-IF architecture, which is suitable for small footprints and low power requirements. The receiver achieves a 3.5 dB NF with a 1 dB compression point of −21 dBm and a gain of 13 dB.
“…High PAPR in 5G transmitters (TX) can impair TX average PAE and cause overheating difficulties. 2,8,9 Signals can be delivered with high data rates in a limited frequency spectrum by using complex modulation methods. The PAPR of signals that use such modulations is extremely high.…”
Section: Introductionmentioning
confidence: 99%
“…In addition, we should also consider high peak‐to‐average‐power‐ratios (PAPR), which means having sporadic peaks that are much higher than the average value of the waveform in the time domain. High PAPR in 5G transmitters (TX) can impair TX average PAE and cause overheating difficulties 2,8,9 …”
In this paper, functionality of the Doherty power amplifiers (DPAs) along with their design constraints such as DPA combining techniques are reviewed. This is because power amplifier (PA) is a key building block in the design of fifth generation (5G) communication systems. A significant trend is the DPA bandwidth enhancement technique, which is the subject of numerous papers in the literature. So, we will review some papers with different solutions to address DPA's bandwidth limitations. There are also different works in the literature that have focused on high-efficiency PA structure designs, which are also discussed in this paper. An excellent option for effective power combining in broadband designs is using balanced amplifiers. We have discussed load modulated balanced amplifiers (LMBA) in this paper because designing an effective PA with a wide bandwidth is crucial. We also covered some papers that have proposed techniques based on the linearization method to bring the efficiency and linearity of DPAs to a fair level.
K E Y W O R D SDoherty power amplifier, energy efficiency, fifth generation (5G), linearization, peak to average power ratio (PAPR), quasi-balanced Doherty power amplifier (QB-DPA)
“…The speed limitations of CMOS devices make it challenging to implement sub-millimeter-wave PAs. Several techniques have been proposed to address these challenges, including capacitive neutralization [ 15 , 16 ], current-combining transformers [ 17 ], direct combining, pulse injection [ 18 ], and Doherty topology [ 19 ].…”
This paper presents a 160 GHz, D-band, low-noise amplifier (LNA) and a D-band power amplifier (PA) implemented in the Global Foundries 22 nm CMOS FDSOI. The two designs are used for the contactless monitoring of vital signs in the D-band. The LNA is based on multiple stages of a cascode amplifier topology with a common source topology adopted as the input and output stages. The input stage of the LNA is designed for simultaneous input and output matching, while the inter-stage-matching networks are designed for maximizing the voltage swing. The LNA achieved a maximum gain of 17 dB at 163 GHz. The input return loss was quite poor in the 157–166 GHz frequency band. The −3 dB gain bandwidth corresponded to 157–166 GHz. The measured noise figure was between 7.6 dB and 8 dB within the −3 dB gain bandwidth. The power amplifier achieved an output 1 dB compression point of 6.8 dBm at 159.75 GHz. The measured power consumptions of the LNA and the PA were 28.8 mW and 10.8 mW, respectively.
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