A 27 GHz double polysilicon bipolar technology on bonded SOI with embedded 58 mu m/sup 2/ CMOS memory cells for ECL-CMOS SRAM applications

Hiramoto,; Tamba,; Yoshida, Minoru; Hashimoto, Y.; Fujiwara,; Watanabe, Toru; Odaka,; Usami,; Ikeda, Kazuhiro

doi:10.1109/iedm.1992.307304

Cited by 17 publications

(4 citation statements)

References 4 publications

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“…The kind of material placed in the deep trench could also increase the possibility of defect occurrence. If polysilicon is used as the trench filling material [32], stress due to cap oxidation can cause crystal defects and/or changes in the BJT characteristics [9], [33]. The combination of low-stress oxide deposition and post annealing prevents this problem.…”

Section: A Optimize Order Of Thermal Processing Stepsmentioning

confidence: 99%

“…Impurity diffusion from heavily doped source/drain (S/D) regions during BJT block processing was adjustable until the 0.25 μm generation. Expanding the MOSFET SW length and adjusting the impurity profile of the halo regions suppress the short channel effects, so the SiGe HBT module can be integrated into the base CMOS process after MOS formation [9], [12], [16]. However, things became more difficult from the 0.18 μm generation.…”

Section: Low Thermal Budget Process For Forming Hbtsmentioning

confidence: 99%

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A Flexible 0.18 $\mu{\rm m}$ BiCMOS Technology Suitable for Various Applications

Hashimoto

Nonaka

Tominari

et al. 2013

IEEE J. Electron Devices Soc.

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Hitachi's SiGe BiCMOS technology, which integrates 0.18 μm CMOS and a SiGe heterojunction bipolar transistor (HBT), does not degrade MOS or bipolar performance. The BiCMOS process is divided into blocks, and the ordering of their processing is optimized so that they do not interfere with each other. Low-thermal-budget SiGe HBT formation is achieved using a minimal-moisture-desorption oxide layer, thereby avoiding disturbing the CMOS process. This technology, which can also be applied to the 0.13 μm generation, has been used for applications ranging from high-speed ones like automotive radar and 40 Gbps optical communication to consumer ones like wireless.

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Section: A Optimize Order Of Thermal Processing Stepsmentioning

confidence: 99%

Section: Low Thermal Budget Process For Forming Hbtsmentioning

confidence: 99%

A Flexible 0.18 $\mu{\rm m}$ BiCMOS Technology Suitable for Various Applications

Hashimoto

Nonaka

Tominari

et al. 2013

IEEE J. Electron Devices Soc.

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“…Silicon-on-insulator (SOI) devices have been of great interest and present better scaling-down properties than that of conventional bulk devices relatively [1][2][3][4]. To improve device performance has resulted in aggressive scaling of device structure.…”

Section: Introductionmentioning

confidence: 99%

An Investigation of Self-heating effect for npn SiGe HBTs Fabricated on thick-film SOI Substrates

Liao

2012

The 1st IEEE Global Conference on Consumer Electronics 2012

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This paper provides a comprehensive analysis of electro-thermal behavior of the SiGe HBTs on SOI substrate based on two dimensional simulations. The impact of electrical behavior based on physical simulation and electrical characterization were analyzed in detail. Various aspects of the optimization of device performances are described. The impact of self-heating effects in device was analyzed in several different areas. All the results are used for designing and optimizing SiGe HBTs on SOI devices performance.

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“…Thick SOI substrates do not directly enhance device performance as thin SOI substrates do, because impurity-diffused well layers are formed on thick SOI substrates in the same way as they are on conventional bulk Si CMOS substrates. However, combining thick SOI substrates with deep trench isolation makes it possible to achieve completely latchup-free CMOS circuit configuration [3]. Since even small noises can affect RF circuit performance, substrate noise transmission should be avoided for maintaining circuit stability.…”

Section: Introductionmentioning

confidence: 99%

A Study on Suppressing Crosstalk Through a Thick SOI Substrate and Deep Trench Isolation

Hashimoto

Satoh

Fujiwara

et al. 2013

IEEE J. Electron Devices Soc.

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Measurement and simulation studies are conducted on transmission crosstalk in thick silicon-on-insulator substrates. This paper focuses on the role of buried oxide layers and deep trench isolation in suppressing crosstalk. With radio frequency coupling paths on substrates depending on noise frequency, a deep trench guides noise signals to substrates and suppresses transmission crosstalk between input and output ports. Good agreement is obtained between electromagnetic field (EM) simulation and measurement results. The EM simulation results suggest different approaches might be used in designing deep trench isolation patterns for a middle resistivity (MR) substrate and a high resistivity (HR) substrate. Deep trench isolation plays a more important role in HR substrates than in MR substrates.

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A 27 GHz double polysilicon bipolar technology on bonded SOI with embedded 58 mu m/sup 2/ CMOS memory cells for ECL-CMOS SRAM applications

Cited by 17 publications

References 4 publications

A Flexible 0.18 $\mu{\rm m}$ BiCMOS Technology Suitable for Various Applications

A Flexible 0.18 $\mu{\rm m}$ BiCMOS Technology Suitable for Various Applications

An Investigation of Self-heating effect for npn SiGe HBTs Fabricated on thick-film SOI Substrates

A Study on Suppressing Crosstalk Through a Thick SOI Substrate and Deep Trench Isolation

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