A 25mW Highly Linear Continuous-Time FIR Equalizer for 25Gb/s Serial Links in 28-nm CMOS

Loi, Fabrizio; Mammei, Enrico; Erba, Simone; Bassi, Matteo; Mazzanti, Andrea

doi:10.1109/tcsi.2017.2682195

Cited by 9 publications

(6 citation statements)

References 31 publications

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“…Table II compares our designed FIR filter with the results of state-of-the art fabricated analog filter designs. Compared to the single FFE equalizers, we report a similar performance in terms of bandwidth and delay values with respect to previously reported full active delay solutions [12], [19]. Passive solutions like [13] and [20] show increased bandwidth but are not area efficient.…”

Section: System Experimentssupporting

confidence: 79%

“…Two main FIR architectures are used in previous designs, respectively direct and distributed FIR implementations. Recent direct FIR implementations can be found in [9], [11], [12] and [19]. The main limiting structure in direct FIR filters is the summation node for all filter taps.…”

Section: System Architecture and Circuitsmentioning

confidence: 99%

“…A widely used approximation is the first order all-pass filter in Eq. ( 4), used in [12], [19] and [24].…”

Section: ) Forward Delay Elementsmentioning

confidence: 99%

“…25 Gbaud with 2 taps [6]) due to the increased complexity compared to state-of-the-art real valued analog FIR filters (e.g. [12], [13]). In this work, we implement an analog FIR filter with both the capability to handle high baudrates (28 Gbaud) and to compensate longer channel responses by employing 5 complex FIR taps.…”

mentioning

confidence: 99%

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Analog I/Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at 112 Gb/s

Verplaetse

Lambrecht

Vanhoecke

et al. 2020

IEEE J. Solid-State Circuits

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We propose a novel implementation of a complex analog equalization filter for the compensation of frequency dependent variations in coherent optical links. The analog compensation filter can be used in coherent-lite optical communication links where digital signal processing (DSP) is removed to limit the complexity and power consumption. In these links, the filter can compensate electrical bandwidth limitations and distortion introduced by chromatic dispersion in the fiber. The complex filter is implemented by combining 4 distributed analog finite impulse response (FIR) filters to obtain the necessary response. The filter delays are implemented using active delay cell structures to create a compact solution. The analog filter is implemented in a 55nm BiCMOS technology and consumes 185 mW core power for 5 complex filter taps. Performance is evaluated using S-parameter measurements, noise and linearity measurements and real-time system experiments using 112 Gb/s 16-QAM modulated signals.

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Section: System Experimentssupporting

confidence: 79%

Section: System Architecture and Circuitsmentioning

confidence: 99%

“…A widely used approximation is the first order all-pass filter in Eq. ( 4), used in [12], [19] and [24].…”

Section: ) Forward Delay Elementsmentioning

confidence: 99%

mentioning

confidence: 99%

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Analog I/Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at 112 Gb/s

Verplaetse

Lambrecht

Vanhoecke

et al. 2020

IEEE J. Solid-State Circuits

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“…However, by optimizing the delay cell design in the same node a significant reduction in the overall power consumption is also reported [38]. Usage of a lower node will help to reduce the power consumption, which may be inferred from [39,40]. Implementation using FinFET technology is also expected to reduce power consumption and improve performance because of a higher transit frequency (f T ) and a lower supply voltage.…”

Section: B Post Layout Simulation Results At 100 Gb/s Data Ratementioning

confidence: 99%

All-Analog Adaptive Equalizer for Coherent Data Center Interconnects

Nambath

Ashok

Manikandan

et al. 2020

J. Lightwave Technol.

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We present the detailed architecture of an allanalog adaptive equalizer for low-power analog signal processing based coherent optical dual-polarization quadrature phase-shift keying transceivers. The proof of concept equalizer uses the constant modulus algorithm for weight coefficient update. The equalizer, implemented in a 130 nm SiGe BiCMOS technology for 100 Gb/s operation, occupies ∼1.4 mm × 1.35 mm area and draws 1 A current from a 2.5 V supply. Its functionality is validated experimentally for data rates up to 40 Gb/s and by using postlayout circuit simulations for data rates up to 100 Gb/s. The equalizer output after processing with a behavioral Costas loopbased carrier phase recovery and compensation module shows bit error rates well within the hard-decision forward error correction limit for 40 Gb/s single-mode fiber links of length up to 10 km. Performance and power consumption of the equalizer are expected to improve when implemented in advanced CMOS or FinFET technologies. The simple architecture of the analog domain equalizer makes it suitable for analog coherent shortreach interconnects with length less than 10 km and carrier wavelengths of either 1310 nm or 1550 nm.

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Low Power Analog Processing for Ultra-High-Speed Receivers With RF Correlation

Lota

Demosthenous

2023

IEEE Access

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Ultra-high-speed data communication receivers (Rxs) conventionally require analog digital converters (ADC)s with high sampling rates which have design challenges in terms of adequate resolution and power. This leads to ultra-high-speed Rxs utilising expensive and bulky high-speed oscilloscopes which are extremely inefficient for demodulation, in terms of power and size. Designing energy-efficient mixedsignal and baseband units for ultra-high-speed Rxs requires a paradigm approach detailed in this paper that circumvents the use of power-hungry ADCs by employing low-power analog processing. The low-power analog Rx employs direct-demodulation with RF correlation using low-power comparators. The Rx is able to support multiple modulations with highest modulation of 16-QAM reported so far for direct-demodulation with RF correlation. Simulations using Matlab, Simulink R2020a® indicate sufficient symbol-error rate (SER) performance at a symbol rate of 8 GS/s for the 71 GHz Urban Micro Cell and 140 GHz indoor channels. Power analysis undertaken with current analog, hybrid and digital beamforming approaches requiring ADCs indicates considerable power savings. This novel approach can be adopted for ultra-high-speed Rxs envisaged for beyond fifth generation (B5G)/sixth generation (6G)/ terahertz (THz) communication without the powerhungry ADCs, leading to low-power integrated design solutions.

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A 25mW Highly Linear Continuous-Time FIR Equalizer for 25Gb/s Serial Links in 28-nm CMOS

Cited by 9 publications

References 31 publications

Analog I/Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at 112 Gb/s

Analog I/Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at 112 Gb/s

All-Analog Adaptive Equalizer for Coherent Data Center Interconnects

Low Power Analog Processing for Ultra-High-Speed Receivers With RF Correlation

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