A 25Gb/s PAM4 transmitter in 90nm CMOS SOI

Abstract

The continuing demand for higher bandwidth in serial interconnects has renewed interest in multi-level signaling schemes [1][2][3]. A PAM4 transmitter implemented in a 90nm SOI technology [4] that operates at a data rate of 12.5GSym/s (25Gb/s) and targets short-range on-board chip-to-chip interconnects is presented.A block diagram of the PAM4 transmitter is shown in Fig. 3.7.1. Clocked at the quarter symbol rate (CK4, 3.125GHz), the 4b MSB D[0:3] and 4b LSB D[4:7] input data are fed to a first set of 2:1 multiplexers and converted into 4 data streams, corresponding to the half-rate (6.25GHz) even and odd data streams of the MSB and LSB, respectively. Each of the 4 data streams then passes a 4b shift register that consists of 4 latches driven at opposite clock phases of the half-rate clock (CK2, 6.25GHz) and implements the delayed data taps of a 4-tap FIR pre-emphasis filter. To set the sign of any pre-emphasis filter tap, each shift register latch output is followed by an XOR gate that selectively inverts the corresponding filter tap. A second set of eight 2:1 multiplexers then converts the half-rate data into full-speed LSB and MSB signals that drive the 4-tap PAM4 output stages. The half-rate clock (CK2, CMLCK2) and quarter-rate clock (CK4) are derived from a full-rate 12.5GHz differential clock input.Given the nominal 1V supply voltage of the 90nm technology used, the maximum differential signaling amplitude is on the order of 1V pp for the implemented conventional current-mode output driver. As a result, the maximum tolerable channel loss for this transmitter is limited to about 10dB at half the symbol frequency, in order to allow reliable signal detection at the receiver. Our experiments based on measured PCB board data shows that a 4-tap FIR transmit pre-emphasis filter that consists of a pre-cursor tap, a main tap and two post-cursor taps is sufficient to equalize channel loss and improve eye opening. Furthermore, the maximum weight of the individual taps is limited to [± 1 /4, ±1, ± 1 /2, ± 1 /4] for the [pre-cursor, main, post-cursor1, post-cursor2] filter taps in order to save area and power.Two logic styles are employed in the transmitter design: static CMOS gates are used in the input multiplexers, the shift registers, and the sign logic because of their high density and low power consumption. CML gates are used in the second multiplexers due to their higher speed operation and lower supply sensitivity. Figure 3.7.2 shows a more detailed view of the second set of multiplexers and the four PAM4 tap output stages. The resolution of the main tap output DAC is 6b (+1b sign) at a quantization of 200µA for the MSB-DAC and 100µA for the LSB-DAC. Each tap output stage is driven by its own multiplexer with the corresponding delayed data from the shift register. A skewed CMOS pre-driver circuit is used to shift the pseudo-differential data input to voltage levels that are compatible with the subsequent CML logic. At 6.25GHz clock frequency, synchronous timing between the half-rate CMOS clock (CK2) and the CML c...

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